A chip-stack structure including a first chip and a second chip located on the first chip is provided. The first chip includes a first substrate, a first interconnect structure, a first pad, and a first contact conductor. The first interconnect structure is located on a first surface of the first substrate. The first pad is located on the first interconnect structure. The first contact conductor is located in the first substrate and exposed on a second surface of the first substrate opposite to the first surface. The second chip includes a second substrate, a second interconnect structure, a second pad, and a second contact conductor. The second interconnect structure is located on the second substrate. The second pad is located on the second interconnect structure. The second contact conductor is located in the second substrate, wherein the first contact conductor is directly physically in contact with the second pad.

Techniques facilitating three-dimensional monolithic vertical field effect transistor logic gates are provided. A logic device can comprise a first vertical transport field effect transistor formed over and adjacent a substrate and a first bonding film deposited over the first vertical transport field effect transistor. The logic device can also comprise a second vertical transport field effect transistor comprising a second bonding film and stacked on the first vertical transport field effect transistor. The second bonding film can affix the second vertical transport field effect transistor to the first vertical transport field effect transistor. In addition, the logic device can comprise one or more monolithic inter-layer vias that extend from first respective portions of the second vertical transport field effect transistor to second respective portions of the first vertical transport field effect transistor and through the first bonding film and the second bonding film.

Techniques facilitating three-dimensional monolithic vertical field effect transistor logic gates are provided. A logic device can comprise a first vertical transport field effect transistor formed over and adjacent a substrate and a first bonding film deposited over the first vertical transport field effect transistor. The logic device can also comprise a second vertical transport field effect transistor comprising a second bonding film and stacked on the first vertical transport field effect transistor. The second bonding film can affix the second vertical transport field effect transistor to the first vertical transport field effect transistor. In addition, the logic device can comprise one or more monolithic inter-layer vias that extend from first respective portions of the second vertical transport field effect transistor to second respective portions of the first vertical transport field effect transistor and through the first bonding film and the second bonding film.

A structure includes a first die and a second die. The first die includes a first oxide bonding layer having a first plurality of bond pads disposed therein and a first seal ring disposed in the first oxide bonding layer. The first oxide bonding layer extends over the first seal ring. The second die includes a second oxide bonding layer having a second plurality of bond pads disposed therein. The first plurality of bond pads is bonded to the second plurality of bond pads. The first oxide bonding layer is bonded to the second oxide bonding layer. An area interposed between the first seal ring and the second oxide bonding layer is free of bond pads.

A structure includes a first die and a second die. The first die includes a first oxide bonding layer having a first plurality of bond pads disposed therein and a first seal ring disposed in the first oxide bonding layer. The first oxide bonding layer extends over the first seal ring. The second die includes a second oxide bonding layer having a second plurality of bond pads disposed therein. The first plurality of bond pads is bonded to the second plurality of bond pads. The first oxide bonding layer is bonded to the second oxide bonding layer. An area interposed between the first seal ring and the second oxide bonding layer is free of bond pads.

A structure includes a first die and a second die. The first die includes a first oxide bonding layer having a first plurality of bond pads disposed therein and a first seal ring disposed in the first oxide bonding layer. The first oxide bonding layer extends over the first seal ring. The second die includes a second oxide bonding layer having a second plurality of bond pads disposed therein. The first plurality of bond pads is bonded to the second plurality of bond pads. The first oxide bonding layer is bonded to the second oxide bonding layer. An area interposed between the first seal ring and the second oxide bonding layer is free of bond pads.

A structure includes a first die and a second die. The first die includes a first oxide bonding layer having a first plurality of bond pads disposed therein and a first seal ring disposed in the first oxide bonding layer. The first oxide bonding layer extends over the first seal ring. The second die includes a second oxide bonding layer having a second plurality of bond pads disposed therein. The first plurality of bond pads is bonded to the second plurality of bond pads. The first oxide bonding layer is bonded to the second oxide bonding layer. An area interposed between the first seal ring and the second oxide bonding layer is free of bond pads.

A Cu.sub.3Sn electrical interconnect and method of making same in an electrical device, such as for hybrid bond 3D-integration of the electrical device with one or more other electrical devices. The method of forming the Cu.sub.3Sn electrical interconnect includes: depositing a Sn layer in the via hole; depositing a Cu layer atop and in contact with the Sn layer; and heating the Sn layer and the Cu layer such that the Sn and Cu layers diffuse together to form a Cu.sub.3Sn interconnect in the via hole. During the heating, a diffusion front between the Sn and Cu layers moves in a direction toward the Cu layer as initially deposited, such that any remaining Cu layer or any voids formed during the diffusion are at an upper region of the formed Cu.sub.3Sn interconnect in the via hole, thereby allowing such voids or remaining material to be easily removed.

A Cu.sub.3Sn electrical interconnect and method of making same in an electrical device, such as for hybrid bond 3D-integration of the electrical device with one or more other electrical devices. The method of forming the Cu.sub.3Sn electrical interconnect includes: depositing a Sn layer in the via hole; depositing a Cu layer atop and in contact with the Sn layer; and heating the Sn layer and the Cu layer such that the Sn and Cu layers diffuse together to form a Cu.sub.3Sn interconnect in the via hole. During the heating, a diffusion front between the Sn and Cu layers moves in a direction toward the Cu layer as initially deposited, such that any remaining Cu layer or any voids formed during the diffusion are at an upper region of the formed Cu.sub.3Sn interconnect in the via hole, thereby allowing such voids or remaining material to be easily removed.

An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.