A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the contact structures on the first substrate, a second substrate having a second set of conductive contact structures, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the contact structures on the second substrate, and a contact-bonded interface between the first and second set of contact structures formed by contact bonding of the first non-metallic region to the second non-metallic region. The contact structures include elongated contact features, such as individual lines or lines connected in a grid, that are non-parallel on the two substrates, making contact at intersections. Alignment tolerances are thus improved while minimizing dishing and parasitic capacitance.

A method includes forming a dielectric layer over a carrier, forming a plurality of bond pads in the dielectric layer, and performing a planarization to level top surfaces of the dielectric layer and the plurality of bond pads with each other. A device die is bonded to the dielectric layer and portions of the plurality of bond pads through hybrid bonding. The device die is encapsulated in an encapsulating material. The carrier is then demounted from the device die and the dielectric layer.

A method includes forming a dielectric layer over a carrier, forming a plurality of bond pads in the dielectric layer, and performing a planarization to level top surfaces of the dielectric layer and the plurality of bond pads with each other. A device die is bonded to the dielectric layer and portions of the plurality of bond pads through hybrid bonding. The device die is encapsulated in an encapsulating material. The carrier is then demounted from the device die and the dielectric layer.

A wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.

A wafer-to-wafer semiconductor device includes a first wafer substrate having a first bonding layer formed on a first bulk substrate layer. A second wafer substrate includes a second bonding layer formed on a second bulk substrate layer. The second bonding layer is bonded to the first bonding layer to define a bonding interface. At least one of the first wafer substrate and the second wafer substrate includes a crack-arresting film layer configured to increase a bonding energy of the bonding interface.

To reduce the influence of noise in the imaging device configured with the plurality of semiconductor chips.

A first semiconductor chip includes a signal input transistor in which an input signal which is a signal corresponding to incident light is input to a control terminal, a reference input transistor which forms a differential pair along with the signal input transistor and in which a reference signal is input to a control terminal, a first signal line which delivers a change in a current flowing in one of the signal input transistor and the reference input transistor as a result of comparison between the input signal and the reference signal when the current is changed in accordance with a difference between the input signal and the reference signal, and a first pad which is electrically connected to the first signal line. A second semiconductor chip includes a processing circuit which processes the result of the comparison, a second signal line which is electrically connected to the processing circuit and delivers the result of the comparison to the processing circuit, and a second pad which is electrically connected to the second signal line and the first pad.

To reduce the influence of noise in the imaging device configured with the plurality of semiconductor chips.

A first semiconductor chip includes a signal input transistor in which an input signal which is a signal corresponding to incident light is input to a control terminal, a reference input transistor which forms a differential pair along with the signal input transistor and in which a reference signal is input to a control terminal, a first signal line which delivers a change in a current flowing in one of the signal input transistor and the reference input transistor as a result of comparison between the input signal and the reference signal when the current is changed in accordance with a difference between the input signal and the reference signal, and a first pad which is electrically connected to the first signal line. A second semiconductor chip includes a processing circuit which processes the result of the comparison, a second signal line which is electrically connected to the processing circuit and delivers the result of the comparison to the processing circuit, and a second pad which is electrically connected to the second signal line and the first pad.

To reduce the influence of noise in the imaging device configured with the plurality of semiconductor chips.

A first semiconductor chip includes a signal input transistor in which an input signal which is a signal corresponding to incident light is input to a control terminal, a reference input transistor which forms a differential pair along with the signal input transistor and in which a reference signal is input to a control terminal, a first signal line which delivers a change in a current flowing in one of the signal input transistor and the reference input transistor as a result of comparison between the input signal and the reference signal when the current is changed in accordance with a difference between the input signal and the reference signal, and a first pad which is electrically connected to the first signal line. A second semiconductor chip includes a processing circuit which processes the result of the comparison, a second signal line which is electrically connected to the processing circuit and delivers the result of the comparison to the processing circuit, and a second pad which is electrically connected to the second signal line and the first pad.

To reduce the influence of noise in the imaging device configured with the plurality of semiconductor chips.

A first semiconductor chip includes a signal input transistor in which an input signal which is a signal corresponding to incident light is input to a control terminal, a reference input transistor which forms a differential pair along with the signal input transistor and in which a reference signal is input to a control terminal, a first signal line which delivers a change in a current flowing in one of the signal input transistor and the reference input transistor as a result of comparison between the input signal and the reference signal when the current is changed in accordance with a difference between the input signal and the reference signal, and a first pad which is electrically connected to the first signal line. A second semiconductor chip includes a processing circuit which processes the result of the comparison, a second signal line which is electrically connected to the processing circuit and delivers the result of the comparison to the processing circuit, and a second pad which is electrically connected to the second signal line and the first pad.

In one aspect, an active electronically scanned array (AESA) tile includes a radiator structure and oxide-bonded semiconductor wafers attached to the radiator structure and comprising a radio frequency (RF) manifold and a beam former. An RF signal path through the oxide-bonded wafers comprises a first portion that propagates toward the beam former and a second portion that propagates parallel to the beam former.