In one aspect, an active electronically scanned array (AESA) tile includes a radiator structure and oxide-bonded semiconductor wafers attached to the radiator structure and comprising a radio frequency (RF) manifold and a beam former. An RF signal path through the oxide-bonded wafers comprises a first portion that propagates toward the beam former and a second portion that propagates parallel to the beam former.

A stacked-chip assembly including an IC chip or die that is electrically interconnected to another chip and/or a substrate by one or more traces that are coupled through sidewalls of the chip. Electrical traces extending over a sidewall of the chip may contact metal traces of one or more die interconnect levels that intersect the chip edge. Following chip fabrication, singulation may expose a metal trace that intersects the chip sidewall. Following singulation, a conductive sidewall interconnect trace formed over the chip sidewall is to couple the exposed trace to a top or bottom side of a chip or substrate. The sidewall interconnect trace may be further coupled to a ground, signal, or power rail. The sidewall interconnect trace may terminate with a bond pad to which another chip, substrate, or wire lead is bonded. The sidewall interconnect trace may terminate at another sidewall location on the same chip or another chip.

A method includes forming a first conductive feature and a second conductive feature, forming a metal pad over and electrically connected to the first conductive feature, and forming a passivation layer covering edge portions of the metal pad, with a center portion of a top surface of the metal pad exposed through an opening in the metal pad. A first dielectric layer is formed to cover the metal pad and the passivation layer. A bond pad is formed over the first dielectric layer, and the bond pad is electrically coupled to the second conductive feature. A second dielectric layer is deposited to encircle the bond pad. A planarization is performed to level a top surface of the second dielectric layer with the bond pad. At a time after the planarization is performed, an entirety of the top surface of the metal pad is in contact with dielectric materials.

A method includes forming a first conductive feature and a second conductive feature, forming a metal pad over and electrically connected to the first conductive feature, and forming a passivation layer covering edge portions of the metal pad, with a center portion of a top surface of the metal pad exposed through an opening in the metal pad. A first dielectric layer is formed to cover the metal pad and the passivation layer. A bond pad is formed over the first dielectric layer, and the bond pad is electrically coupled to the second conductive feature. A second dielectric layer is deposited to encircle the bond pad. A planarization is performed to level a top surface of the second dielectric layer with the bond pad. At a time after the planarization is performed, an entirety of the top surface of the metal pad is in contact with dielectric materials.

An LED flip-chip structure is provided, wherein a silica gel, a fluorescent glue, a lens, an anti-reflection film and a packaging adhesive layer is sequentially arranged on the LED chip. The silica gel and fluorescent glue are sequentially filled within an insulating reflective cup, outside which a metal reflective cup and a light absorption layer is sequentially provided. The packaging adhesive layer is filled between the reflective cup and the lens. A sapphire substrate is pretreated to form an inverted T-shaped structure, on which a layer of epitaxial wafer of ceramic film is grown, and then a layer of high temperature resistant conductive film is grown on upper surfaces of grooves at both sides. A protrusion of the inverted T-shaped structure is uniformly coated with a thermally conductive adhesive with a certain thickness.

A capacitive isolation system, capacitive isolator, and method of operating the same are disclosed. The capacitive isolation system is described to include a first semiconductor die and a second semiconductor die each having capacitive elements established thereon and positioned in a face-to-face configuration. An isolation layer is provided between the first and second semiconductor die so as to establish an isolation boundary therebetween. Capacitive coupling is used to carry information across the isolation boundary.

A capacitive isolation system, capacitive isolator, and method of operating the same are disclosed. The capacitive isolation system is described to include a first semiconductor die and a second semiconductor die each having capacitive elements established thereon and positioned in a face-to-face configuration. An isolation layer is provided between the first and second semiconductor die so as to establish an isolation boundary therebetween. Capacitive coupling is used to carry information across the isolation boundary.

A first semiconductor structure including a first bonding oxide layer having a first metallic bonding structure embedded therein and a second semiconductor structure including a second bonding oxide layer having a second metallic bonding structure embedded therein are provided. A nitride surface treatment process is performed to provide a nitrided surface layer to each structure. Each nitrided surface layer includes nitridized oxide regions located in an upper portion of the bonding oxide layer and nitridized metallic regions located in an upper portion of the metallic bonding structures. The nitrogen within the nitridized metallic regions is then removed to restore the upper portion of the metallic bonding structures to its original composition. Bonding is performed to form a dielectric bonding interface between the nitridized oxide regions present in the first and second structures, and a metallic bonding interface between the first and second metallic bonding structures.

A first semiconductor structure including a first bonding oxide layer having a first metallic bonding structure embedded therein and a second semiconductor structure including a second bonding oxide layer having a second metallic bonding structure embedded therein are provided. A nitride surface treatment process is performed to provide a nitrided surface layer to each structure. Each nitrided surface layer includes nitridized oxide regions located in an upper portion of the bonding oxide layer and nitridized metallic regions located in an upper portion of the metallic bonding structures. The nitrogen within the nitridized metallic regions is then removed to restore the upper portion of the metallic bonding structures to its original composition. Bonding is performed to form a dielectric bonding interface between the nitridized oxide regions present in the first and second structures, and a metallic bonding interface between the first and second metallic bonding structures.

An integrated circuit includes a first chip bonded to a second chip. The first chip includes gate all around transistors on a substrate. The first chip includes backside conductive vias extending through the substrate to the gate all around transistors. The second chip includes electronic circuitry electrically connected to the transistors by the backside conductive vias.