A wafer laminating method includes a cooling step of cooling a first wafer, a laminating step of producing a laminated wafer by stacking and laminating a second wafer on a surface of the first wafer when condensation forms on the surface of the cooled first wafer, and a heat treatment step of subjecting the laminated wafer to heat treatment.

A wafer laminating method includes a cooling step of cooling a first wafer, a laminating step of producing a laminated wafer by stacking and laminating a second wafer on a surface of the first wafer when condensation forms on the surface of the cooled first wafer, and a heat treatment step of subjecting the laminated wafer to heat treatment.

A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a chip over a first surface of the first substrate. The chip package structure includes a barrier layer over a second surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer and passing through the insulating layer and the barrier layer to connect with the conductive via structure. The chip package structure includes a conductive bump over the conductive pad.

A method includes bonding a first device die with a second device die. The second device die is over the first device die. A passive device is formed in a combined structure including the first and the second device dies. The passive device includes a first and a second end. A gap-filling material is formed over the first device die, with the gap-filling material including portions on opposite sides of the second device die. The method further includes performing a planarization to reveal the second device die, with a remaining portion of the gap-filling material forming an isolation region, forming a first and a second through-vias penetrating through the isolation region to electrically couple to the first device die, and forming a first and a second electrical connectors electrically coupling to the first end and the second end of the passive device.

A method includes bonding a first device die with a second device die. The second device die is over the first device die. A passive device is formed in a combined structure including the first and the second device dies. The passive device includes a first and a second end. A gap-filling material is formed over the first device die, with the gap-filling material including portions on opposite sides of the second device die. The method further includes performing a planarization to reveal the second device die, with a remaining portion of the gap-filling material forming an isolation region, forming a first and a second through-vias penetrating through the isolation region to electrically couple to the first device die, and forming a first and a second electrical connectors electrically coupling to the first end and the second end of the passive device.

An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more inter connect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.

An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more inter connect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.

A semiconductor device provided with a substrate made of material except for semiconductors and having thermal conductivity greater than that of the semiconductor material. The semiconductor device provides, on the support, a metal layer, a primary mesa, and electrodes formed on the primary mesa. The metal layer, which is in contact with the primary mesa, may be made of at least one of tungsten (W), molybdenum (Mo), and tantalum (Ta) with a thickness of the 10 to 60 nm.

A semiconductor device provided with a substrate made of material except for semiconductors and having thermal conductivity greater than that of the semiconductor material. The semiconductor device provides, on the support, a metal layer, a primary mesa, and electrodes formed on the primary mesa. The metal layer, which is in contact with the primary mesa, may be made of at least one of tungsten (W), molybdenum (Mo), and tantalum (Ta) with a thickness of the 10 to 60 nm.

A memory device including at least one dummy word line over a substrate; a plurality of word lines over the dummy word line; and a plurality of vertical holes extending through the at least one dummy word line and the plurality of word lines in a direction perpendicular to the substrate and classified into channel holes and dummy holes, each of the channel holes being connected to a bit line. The method including performing an erase operation on dummy cells formed as the dummy word line and the dummy holes; verifying the erase operation; and performing a program operation on at least one of the dummy cells such that the at least one dummy cell has a higher threshold voltage than main cells formed as the dummy word line and the channel holes.