H01L2224/11

PACKAGE STRUCTURES

A package structure including a bottom die, a first die, a second die, an encapsulant and a first dummy structure is provided. The first die and a second die are bonded to a first side of the bottom die. The encapsulant laterally encapsulates the first die and the second die. The first dummy structure is bonded to the first side of the bottom die, wherein a sidewall of the first dummy structure is coplanar with a first sidewall of the bottom die.

Composition for cobalt or cobalt alloy electroplating

A cobalt electroplating composition may include (a) cobalt ions; and (b) an ammonium compound of formula (NR.sup.1R.sup.2R.sup.3H.sup.+).sub.nX.sup.n−, wherein R.sup.1, R.sup.2, R.sup.3 are independently H or linear or branched C.sub.1 to C.sub.6 alkyl, X is one or more n valent inorganic or organic counter ion(s), and n is an integer from 1, 2, or 3.

Composition for cobalt or cobalt alloy electroplating

A cobalt electroplating composition may include (a) cobalt ions; and (b) an ammonium compound of formula (NR.sup.1R.sup.2R.sup.3H.sup.+).sub.nX.sup.n−, wherein R.sup.1, R.sup.2, R.sup.3 are independently H or linear or branched C.sub.1 to C.sub.6 alkyl, X is one or more n valent inorganic or organic counter ion(s), and n is an integer from 1, 2, or 3.

Semiconductor structure and method of forming semiconductor package

The present disclosure provides a semiconductor structure, including a capacitor. The capacitor includes a first electrode and a second electrode respectively electrically connected to a first conductor and a second conductor; and a first dielectric layer between the first electrode and the second electrode. In some embodiments, the first dielectric layer contacts with a sidewall surface of the first conductor. The semiconductor structure further includes a second dielectric layer over and adjacent to the capacitor. A method of forming the semiconductor package is also provided.

Method for fabricating semiconductor device with EMI protection structure
11587885 · 2023-02-21 · ·

The present disclosure provides a method for fabricating a semiconductor device including providing a first semiconductor die, forming a connection dielectric layer above the first semiconductor die, forming a first bottom protection layer in the connection dielectric layer, forming a first conductive plate on the first bottom protection layer, and forming a first top protection layer on the first conductive plate. The first bottom protection layer and the first top protection layer are formed of manganese-zinc ferrite, nickel-zinc ferrite, cobalt ferrite, strontium ferrite, barium ferrite, lithium ferrite, lithium-zinc ferrite, single crystal yttrium iron garnet, or gallium substituted single crystal yttrium iron garnet.

Method for fabricating semiconductor device with EMI protection structure
11587885 · 2023-02-21 · ·

The present disclosure provides a method for fabricating a semiconductor device including providing a first semiconductor die, forming a connection dielectric layer above the first semiconductor die, forming a first bottom protection layer in the connection dielectric layer, forming a first conductive plate on the first bottom protection layer, and forming a first top protection layer on the first conductive plate. The first bottom protection layer and the first top protection layer are formed of manganese-zinc ferrite, nickel-zinc ferrite, cobalt ferrite, strontium ferrite, barium ferrite, lithium ferrite, lithium-zinc ferrite, single crystal yttrium iron garnet, or gallium substituted single crystal yttrium iron garnet.

Transferrable pillar structure for fanout package or interconnect bridge

A pillar structure is provided. The pillar structure includes a plurality of pillars. Each of the pillars include a capping material layer formed in a pit etched into a template wafer, a conductive plug formed on the capping material layer, a base layer formed on the conductive plug, and an attach material layer formed on the base layer. The pillars are joined vertically together to form the pillar structure.

METHOD FOR FABRICATING HYBRID BONDED STRUCTURE

A hybrid bonded structure including a first integrated circuit component and a second integrated circuit component is provided. The first integrated circuit component includes a first dielectric layer, first conductors and isolation structures. The first conductors and the isolation structures are embedded in the first dielectric layer. The isolation structures are electrically insulated from the first conductors and surround the first conductors. The second integrated circuit component includes a second dielectric layer and second conductors. The second conductors are embedded in the second dielectric layer. The first dielectric layer is bonded to the second dielectric layer and the first conductors are bonded to the second conductors.

METHOD FOR FABRICATING HYBRID BONDED STRUCTURE

A hybrid bonded structure including a first integrated circuit component and a second integrated circuit component is provided. The first integrated circuit component includes a first dielectric layer, first conductors and isolation structures. The first conductors and the isolation structures are embedded in the first dielectric layer. The isolation structures are electrically insulated from the first conductors and surround the first conductors. The second integrated circuit component includes a second dielectric layer and second conductors. The second conductors are embedded in the second dielectric layer. The first dielectric layer is bonded to the second dielectric layer and the first conductors are bonded to the second conductors.

PACKAGE AND MANUFACTURING METHOD THEREOF

A package includes a first package structure and a second package structure stacked on the first package structure. The first package structure includes a redistribution structure, an integrated circuit, an encapsulant, and conductive structures. The integrated circuit is disposed on the redistribution structure and includes a first chip, a second chip, a third chip, and a fourth chip. The first chip includes a semiconductor substrate that extends continuously throughout the first chip. The second and the third chips are disposed side by side on the first chip. The fourth chip is disposed over the first chip and includes a semiconductor substrate that extends continuously throughout the fourth chip. Sidewalls of the first chip are aligned with sidewalls of the fourth chip. The encapsulant laterally encapsulates the integrated circuit. The conductive structures penetrate through the encapsulant. The second package structure is electrically connected to the redistribution structure through the conductive structures.