A semiconductor device includes a substrate having a circuit region and a peripheral region disposed around and enclosing the circuit region in a plan view, a first interconnect layer formed on the substrate, a second interconnect layer formed on the first interconnect layer, a third interconnect layer formed on the second interconnect layer, and a guard ring formed in the peripheral region, wherein the guard ring includes a first interconnect formed in the first interconnect layer, and disposed around and enclosing the circuit region in a plan view, a second interconnect formed in the third interconnect layer, and disposed around and enclosing the circuit region in a plan view, and a first via connected to the first interconnect and to the second interconnect, and disposed in a groove shape along a perimeter edge of the substrate in a plan view.

The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a thermally conductive film, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The thermally conductive film, which has a thermal conductivity greater than 10 W/m.Math.K and an electrical resistivity greater than 1E5 Ohm-cm, resides between the active layer and the first mold compound. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.

The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a thermally conductive film, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The thermally conductive film, which has a thermal conductivity greater than 10 W/m.Math.K and an electrical resistivity greater than 1E5 Ohm-cm, resides between the active layer and the first mold compound. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.

A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.

A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.

A microelectronic device is formed by dispensing discrete amounts of a mixture of photoresist resin and solvents from droplet-on-demand sites onto a wafer to form a first photoresist sublayer, while the wafer is at a first temperature which allows the photoresist resin to attain less than 10 percent thickness non-uniformity. The wafer moves under the droplet-on-demand sites in a first direction to form the first photoresist sublayer. A portion of the solvents in the first photoresist sublayer is removed. A second photoresist sublayer is formed on the first photoresist sublayer using the droplet-on-demand sites while the wafer is at a second temperature to attain less than 10 percent thickness non-uniformity in the combined first and second photoresist sublayers. The wafer moves under the droplet-on-demand sites in a second direction for the second photoresist sublayer, opposite from the first direction.

A microelectronic device is formed by dispensing discrete amounts of a mixture of photoresist resin and solvents from droplet-on-demand sites onto a wafer to form a first photoresist sublayer, while the wafer is at a first temperature which allows the photoresist resin to attain less than 10 percent thickness non-uniformity. The wafer moves under the droplet-on-demand sites in a first direction to form the first photoresist sublayer. A portion of the solvents in the first photoresist sublayer is removed. A second photoresist sublayer is formed on the first photoresist sublayer using the droplet-on-demand sites while the wafer is at a second temperature to attain less than 10 percent thickness non-uniformity in the combined first and second photoresist sublayers. The wafer moves under the droplet-on-demand sites in a second direction for the second photoresist sublayer, opposite from the first direction.

In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.

An integrated fan-out structure on a semiconductor die, method of making the same and method of testing the semiconductor die are disclosed. The semiconductor die includes a bond pad and a hole formed in the bond pad, a passivation layer formed over a portion of the bond pad, and a protective layer formed over the hole in the bond pad.

A flip chip package unit and associated packaging method. The flip chip package unit may include an integrated circuit (“IC”) die having a plurality of metal pillars formed on its first surface and attached to a rewiring substrate with the first surface of the IC die facing to the rewiring substrate, an under-fill material filling gaps between the first surface of the IC die and the rewiring substrate, and a thermal conductive protection film covering or overlaying and directly contacting with the entire second die surface and a first portion of sidewalls of the IC die. The thermal conductive protection film may have good thermal conductivity, uneasy to fall off from the IC die and can provide physical protection, electromagnetic interference protection and effective heat dissipation path to the IC die.