A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.

A package comprising a substrate and an integrated device coupled to the substrate through a plurality of pillar interconnects and a plurality of solder interconnects. The plurality of pillar interconnects comprises a first pillar interconnect. The first pillar interconnect comprises a first pillar interconnect portion comprising a first width and a second pillar interconnect portion comprising a second width that is different than the first width.

A package comprising a substrate and an integrated device coupled to the substrate through a plurality of pillar interconnects and a plurality of solder interconnects. The plurality of pillar interconnects comprises a first pillar interconnect. The first pillar interconnect comprises a first pillar interconnect portion comprising a first width and a second pillar interconnect portion comprising a second width that is different than the first width.

An object is to allow for simple measurement of a bump height. There is provided a device for measuring a bump height comprising: a light sensor provided with a light source and a light-receiving element and configured to irradiate a substrate including a seed layer, a resist layer formed on the seed layer and a bump formed in an opening of the resist layer, with light emitted from the light source and to detect reflected light that is reflected from the seed layer via the resist layer and reflected light that is reflected from the bump, by the light-receiving element; and a control device configured to calculate a height of the bump relative to the seed layer, based on the reflected light from the seed layer and the reflected light from the bump and to subtract an error caused by a refractive index of the resist layer from the height of the bump calculated based on the reflected lights, so as to correct the height of the bump.

An object is to allow for simple measurement of a bump height. There is provided a device for measuring a bump height comprising: a light sensor provided with a light source and a light-receiving element and configured to irradiate a substrate including a seed layer, a resist layer formed on the seed layer and a bump formed in an opening of the resist layer, with light emitted from the light source and to detect reflected light that is reflected from the seed layer via the resist layer and reflected light that is reflected from the bump, by the light-receiving element; and a control device configured to calculate a height of the bump relative to the seed layer, based on the reflected light from the seed layer and the reflected light from the bump and to subtract an error caused by a refractive index of the resist layer from the height of the bump calculated based on the reflected lights, so as to correct the height of the bump.

A device is provided. The device includes a bridge layer over a first substrate. A first connector electrically connecting the bridge layer to the first substrate. A first die is coupled to the bridge layer and the first substrate, and a second die is coupled to the bridge layer.

A device is provided. The device includes a bridge layer over a first substrate. A first connector electrically connecting the bridge layer to the first substrate. A first die is coupled to the bridge layer and the first substrate, and a second die is coupled to the bridge layer.

A method includes forming a metal bump on a top surface of a first package component, forming a solder region on a top surface of the metal bump, forming a protection layer extending on a sidewall of the metal bump, reflowing the solder region to bond the first package component to a second package component, and dispensing an underfill between the first package component and the second package component. The underfill is in contact with the protection layer.

A method includes forming a metal bump on a top surface of a first package component, forming a solder region on a top surface of the metal bump, forming a protection layer extending on a sidewall of the metal bump, reflowing the solder region to bond the first package component to a second package component, and dispensing an underfill between the first package component and the second package component. The underfill is in contact with the protection layer.

A manufacturing method of a chip package structure includes the following steps. A plurality of chips is disposed on a first insulating layer. The back surface of each of the chips is in direct contact with the first insulating layer. A stress buffer layer is formed to extend and cover the active surface and the peripheral surface of each of the chips, and a bottom surface of the stress buffer layer is aligned with the back surface of each of the chips. The stress buffer layer has an opening exposing a part of the active surface of each of the chips, and the redistribution layer is electrically connected to each of the chips through the opening. A plurality of solder balls is electrically connected to the redistribution layer exposed by the blind holes. A singularizing process is performed to form a plurality of chip package structures separated from each other.