An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.

An endoscope device includes: an imaging unit including a semiconductor chip including an image sensor formed thereon, and a protective glass adhered on the image sensor with an adhesive layer; and a holder configured to hold the imaging unit by fitting the protective glass therein. The semiconductor chip includes: a light-receiving section; a peripheral circuit section; a guard ring surrounding the light-receiving section and the peripheral circuit section; and a plurality of metal dots formed on an outer circumference of the guard ring. The protective glass is adhered to the semiconductor chip by the adhesive layer so as to cover the light-receiving section, the peripheral circuit section, the guard ring, and the metal dots, and the metal dots are formed at a same interval from the outer circumference of the guard ring to a connection end portion of a connecting surface between the semiconductor chip and the protective glass.

An integrated circuit (IC) package is disclosed that contains high density interconnects to connect multiple dies. The IC package includes an encapsulated layer, a first dielectric layer, and a second dielectric layer. The encapsulated layer forms the base of the IC package and includes the multiple dies. The first dielectric layer positioned between the encapsulated layer and the second layer. The first dielectric layer includes vias to connect to the input/ouput pads of active surfaces of the multiple dies. The second dielectric layer includes interconnect layers where at least one of the interconnect layers forms an electrical path to connect at least two of the multiple dies together. According to embodiments of the present disclosure, the IC package enables a high manufacturing yield due to large tolerances allowed for selection of dies. Embodiments of the present disclosure also increase an amount of input/output interconnection between multiple dies in the IC package. Embodiments of the present disclosure further enable lower manufacturing costs because of the use of mature reconstituted dies and redistribution layer technologies and the lack of a need for an interposer to connect multiple dies.

An integrated circuit (IC) package is disclosed that contains high density interconnects to connect multiple dies. The IC package includes an encapsulated layer, a first dielectric layer, and a second dielectric layer. The encapsulated layer forms the base of the IC package and includes the multiple dies. The first dielectric layer positioned between the encapsulated layer and the second layer. The first dielectric layer includes vias to connect to the input/ouput pads of active surfaces of the multiple dies. The second dielectric layer includes interconnect layers where at least one of the interconnect layers forms an electrical path to connect at least two of the multiple dies together. According to embodiments of the present disclosure, the IC package enables a high manufacturing yield due to large tolerances allowed for selection of dies. Embodiments of the present disclosure also increase an amount of input/output interconnection between multiple dies in the IC package. Embodiments of the present disclosure further enable lower manufacturing costs because of the use of mature reconstituted dies and redistribution layer technologies and the lack of a need for an interposer to connect multiple dies.

Some implementations provide a device that includes a passive component and a substrate coupled to the passive component, where a surface of the substrate comprises a first irradiated portion. In some implementations, the first irradiated portion is located in an offset portion of the substrate. Some implementations provide an integrated device that includes a device layer and a substrate coupled to the device layer, where a surface of the substrate comprises a first irradiated portion. In some implementations, the first irradiated portion is located in an offset portion of the substrate.

Some implementations provide a device that includes a passive component and a substrate coupled to the passive component, where a surface of the substrate comprises a first irradiated portion. In some implementations, the first irradiated portion is located in an offset portion of the substrate. Some implementations provide an integrated device that includes a device layer and a substrate coupled to the device layer, where a surface of the substrate comprises a first irradiated portion. In some implementations, the first irradiated portion is located in an offset portion of the substrate.

A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

A semiconductor device having an electrode type of the ball grid array (BGA) and a process of forming the electrode are disclosed. The electrode insulating film, a seed layer on the insulating film, a mound metal on the insulating film and an interconnection on the seed layer. The mound metal surrounds the seed layer without forming any gap therebetween. The interconnection, which is formed by electroless plating, is apart from the insulating film with the mound metal as an extension barrier for the plating.

A semiconductor device has a temporary carrier. A semiconductor die is oriented with an active surface toward, and mounted to, the temporary carrier. An encapsulant is deposited with a first surface over the temporary carrier and a second surface, opposite the first surface, is deposited over a backside of the semiconductor die. The temporary carrier is removed. A portion of the encapsulant in a periphery of the semiconductor die is removed to form an opening in the first surface of the encapsulant. An interconnect structure is formed over the active surface of the semiconductor die and extends into the opening in the encapsulant layer. A via is formed and extends from the second surface of the encapsulant to the opening. A first bump is formed in the via and electrically connects to the interconnect structure.