A semiconductor device including: a first formation site and a second formation site for forming a first conductive bump and a second conductive bump; when a first environmental density corresponding to the first formation site is greater than a second environmental density corresponding to the second formation site, a cross sectional area of the second formation site is greater than a cross sectional area of the first formation site; wherein the first environmental density is determined by a number of formation sites around the first formation site in a predetermined range and the second environmental density is determined by a number of formation sites around the second formation site in the predetermined range; wherein a first area having the first environmental density forms an ellipse layout while a second area having the second environmental density forms a strip layout surrounding the ellipse layout.

A semiconductor device including: a first formation site and a second formation site for forming a first conductive bump and a second conductive bump; when a first environmental density corresponding to the first formation site is greater than a second environmental density corresponding to the second formation site, a cross sectional area of the second formation site is greater than a cross sectional area of the first formation site; wherein the first environmental density is determined by a number of formation sites around the first formation site in a predetermined range and the second environmental density is determined by a number of formation sites around the second formation site in the predetermined range; wherein a first area having the first environmental density forms an ellipse layout while a second area having the second environmental density forms a strip layout surrounding the ellipse layout.

A method includes forming a metal bump on a top surface of a first package component, forming a solder region on a top surface of the metal bump, forming a protection layer extending on a sidewall of the metal bump, reflowing the solder region to bond the first package component to a second package component, and dispensing an underfill between the first package component and the second package component. The underfill is in contact with the protection layer.

A method includes forming a metal bump on a top surface of a first package component, forming a solder region on a top surface of the metal bump, forming a protection layer extending on a sidewall of the metal bump, reflowing the solder region to bond the first package component to a second package component, and dispensing an underfill between the first package component and the second package component. The underfill is in contact with the protection layer.

A technical object of the present invention is to devise a glass sheet that facilitates position alignment with a substrate to be processed and is less liable to be broken during conveyance, or processing treatment of the substrate to be processed, to thereby contribute to an increase in density of a semiconductor package. In order to achieve the technical object, the glass sheet of the present invention includes, in a contour thereof: a contour portion; and a position alignment portion, in which all or part of an end edge region of the position alignment portion where a surface thereof and an end surface thereof intersect is chamfered.

A technical object of the present invention is to devise a glass sheet that facilitates position alignment with a substrate to be processed and is less liable to be broken during conveyance, or processing treatment of the substrate to be processed, to thereby contribute to an increase in density of a semiconductor package. In order to achieve the technical object, the glass sheet of the present invention includes, in a contour thereof: a contour portion; and a position alignment portion, in which all or part of an end edge region of the position alignment portion where a surface thereof and an end surface thereof intersect is chamfered.

A manufacturing method of a chip package structure includes the following steps. A plurality of chips is disposed on a first insulating layer. The back surface of each of the chips is in direct contact with the first insulating layer. A stress buffer layer is formed to extend and cover the active surface and the peripheral surface of each of the chips, and a bottom surface of the stress buffer layer is aligned with the back surface of each of the chips. The stress buffer layer has an opening exposing a part of the active surface of each of the chips, and the redistribution layer is electrically connected to each of the chips through the opening. A plurality of solder balls is electrically connected to the redistribution layer exposed by the blind holes. A singularizing process is performed to form a plurality of chip package structures separated from each other.

A chip structure is provided. The chip structure includes a substrate. The clip structure includes a conductive line over the substrate. The chip structure includes a first passivation layer over the substrate and the conductive line. The chip structure includes a conductive pad over the first passivation layer covering the conductive line. The conductive pad is thicker and wider than the conductive line. The chip structure includes a first conductive via structure and a second conductive via structure passing through the first passivation layer and directly connected between the conductive pad and the conductive line. The chip structure includes a conductive pillar over the conductive pad.

The present disclosure provides a method for manufacturing a semiconductor structure, including patterning a photo-sensitive polymer layer with a plurality of trenches by a first mask, the first mask having a first line pitch, patterning a photoresist positioning on a mesa between adjacent trenches by a second mask, the second mask having a second line pitch, the first mask and the second mask having substantially identical pattern topography, and the second line pitch being greater than the first line pitch, and selectively plating conductive material in the plurality of trenches.

A semiconductor light detection element has a plurality of channels, each of which consists of a photodiode array including a plurality of avalanche photodiodes operating in Geiger mode, quenching resistors connected in series to the respective avalanche photodiodes, and signal lines to which the quenching resistors are connected in parallel. A mounting substrate is configured so that a plurality of electrodes corresponding to the respective channels are arranged on a third principal surface side and so that a signal processing unit for processing output signals from the respective channels is arranged on a fourth principal surface side. In a semiconductor substrate, through-hole electrodes electrically connected to the signal lines are formed for the respective channels. The through-hole electrodes and the electrodes are electrically connected through bump electrodes.