The present disclosure relates to a radio frequency (RF) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes an isolation portion, a back-end-of-line (BEOL) portion, and a front-end-of-line (FEOL) portion with a contact layer and an active section. The contact layer resides over the BEOL portion, the active section resides over the contact layer, and the isolation portion resides over the contact layer to encapsulate the active section. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the isolation portion of the thinned device die.

The present disclosure relates to a radio frequency (RF) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes an isolation portion, a back-end-of-line (BEOL) portion, and a front-end-of-line (FEOL) portion with a contact layer and an active section. The contact layer resides over the BEOL portion, the active section resides over the contact layer, and the isolation portion resides over the contact layer to encapsulate the active section. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the isolation portion of the thinned device die.

A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die. The first IC die includes a first semiconductor substrate and a first interconnect structure over the first semiconductor substrate. The second IC die includes a second semiconductor substrate and a second interconnect structure over the second semiconductor substrate. A plurality of electrical coupling structures is arranged at the peripheral region of the first semiconductor device and the second semiconductor device. The plurality of electrical coupling structures respectively comprises a through silicon via (TSV) disposed in the second semiconductor substrate and electrically coupled to the first semiconductor device through a stack of wiring layers and inter-wire vias.

A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die. The first IC die includes a first semiconductor substrate and a first interconnect structure over the first semiconductor substrate. The second IC die includes a second semiconductor substrate and a second interconnect structure over the second semiconductor substrate. A plurality of electrical coupling structures is arranged at the peripheral region of the first semiconductor device and the second semiconductor device. The plurality of electrical coupling structures respectively comprises a through silicon via (TSV) disposed in the second semiconductor substrate and electrically coupled to the first semiconductor device through a stack of wiring layers and inter-wire vias.

A semiconductor package according to the inventive concept includes a first semiconductor chip configured to include a first semiconductor device, a first semiconductor substrate, a plurality of through electrodes penetrating the first semiconductor substrate, and a plurality of first chip connection pads arranged on an upper surface of the first semiconductor substrate; a plurality of second semiconductor chips sequentially stacked on an upper surface of the first semiconductor chip and configured to each include a second semiconductor substrate, a second semiconductor device controlled by the first semiconductor chip, and a plurality of second chip connection pads arranged on an upper surface of the second semiconductor substrate; a plurality of bonding wires configured to connect the plurality of first chip connection pads to the plurality of second chip connection pads; and a plurality of external connection terminals arranged on a lower surface of the first semiconductor chip.

A semiconductor package according to the inventive concept includes a first semiconductor chip configured to include a first semiconductor device, a first semiconductor substrate, a plurality of through electrodes penetrating the first semiconductor substrate, and a plurality of first chip connection pads arranged on an upper surface of the first semiconductor substrate; a plurality of second semiconductor chips sequentially stacked on an upper surface of the first semiconductor chip and configured to each include a second semiconductor substrate, a second semiconductor device controlled by the first semiconductor chip, and a plurality of second chip connection pads arranged on an upper surface of the second semiconductor substrate; a plurality of bonding wires configured to connect the plurality of first chip connection pads to the plurality of second chip connection pads; and a plurality of external connection terminals arranged on a lower surface of the first semiconductor chip.

A package that includes a first integrated device comprising a first plurality of interconnects; a plurality of solder interconnects coupled to the first plurality of interconnects; a second integrated device comprising a second plurality of interconnects, wherein the second integrated device is coupled to the first integrated device through the second plurality of interconnects, the plurality of solder interconnects and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; and a plurality of spacer balls located between the first integrated device and the second integrated device.

A package that includes a first integrated device comprising a first plurality of interconnects; a plurality of solder interconnects coupled to the first plurality of interconnects; a second integrated device comprising a second plurality of interconnects, wherein the second integrated device is coupled to the first integrated device through the second plurality of interconnects, the plurality of solder interconnects and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; and a plurality of spacer balls located between the first integrated device and the second integrated device.

Processing methods may be performed to form a fan-out interconnect structure. The methods may include forming a semiconductor active device structure overlying a first substrate. The semiconductor active device structure may include first conductive contacts. The methods may include forming an interconnect structure overlying a second substrate. The interconnect structure may include second conductive contacts. The methods may also include joining the first substrate with the second substrate. The joining may include coupling the first conductive contacts with the second conductive contacts. The interconnect structure may extend beyond the lateral dimensions of the semiconductor active device structure.

Processing methods may be performed to form a fan-out interconnect structure. The methods may include forming a semiconductor active device structure overlying a first substrate. The semiconductor active device structure may include first conductive contacts. The methods may include forming an interconnect structure overlying a second substrate. The interconnect structure may include second conductive contacts. The methods may also include joining the first substrate with the second substrate. The joining may include coupling the first conductive contacts with the second conductive contacts. The interconnect structure may extend beyond the lateral dimensions of the semiconductor active device structure.