A bonding wire for a high-speed signal line for connecting a pad electrode of a semiconductor device and a lead electrode on a circuit board contains palladium (Pd), platinum (Pt), silver (Ag), and a trace additive element.

A bonding wire for a semiconductor device, characterized in that the bonding wire includes a Cu alloy core material and a Pd coating layer formed on a surface of the Cu alloy core material, the bonding wire contains an element that provides bonding reliability in a high-temperature environment, and a strength ratio defined by the following Equation (1) is 1.1 to 1.6:

Strength ratio=ultimate strength/0.2% offset yield strength.(1)

A bonding wire for a semiconductor device, characterized in that the bonding wire includes a Cu alloy core material and a Pd coating layer formed on a surface of the Cu alloy core material, the bonding wire contains an element that provides bonding reliability in a high-temperature environment, and a strength ratio defined by the following Equation (1) is 1.1 to 1.6:

Strength ratio=ultimate strength/0.2% offset yield strength.(1)

A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.

An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, a third bonding pad structure, a first internal bonding wire, and a second internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The third bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the third bonding pad structure via the first internal bonding wire. The third bonding pad structure is electrically coupled to the second bonding pad structure via the second internal bonding wire.

An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, a third bonding pad structure, a first internal bonding wire, and a second internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The third bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the third bonding pad structure via the first internal bonding wire. The third bonding pad structure is electrically coupled to the second bonding pad structure via the second internal bonding wire.

First and second layers of different adhesive materials are laminated to a carrier such that the second adhesive layer is attached to the carrier. The first adhesive layer is cured first. A semiconductor die is then placed on the cured first adhesive layer. An encapsulant layer is formed over at least a portion of the cured first adhesive layer while encapsulating the first semiconductor die. The second adhesive layer is cured after which the carrier is separated from the cured second adhesive layer.

A bonding wire for a semiconductor device including a coating layer having Pd as a main component on the surface of a Cu alloy core material and a skin alloy layer containing Au and Pd on the surface of the coating layer has a Cu concentration of 1 to 10 at % at an outermost surface thereof and has the core material containing a metallic element of Group 10 of the Periodic Table of Elements in a total amount of 0.1 to 3.0% by mass, thereby achieving improvement in 2nd bondability and excellent ball bondability in a high-humidity heating condition. Furthermore, a maximum concentration of Au in the skin alloy layer is preferably 15 at % to 75 at %.

A bonding wire for a semiconductor device including a coating layer having Pd as a main component on the surface of a Cu alloy core material and a skin alloy layer containing Au and Pd on the surface of the coating layer has a Cu concentration of 1 to 10 at % at an outermost surface thereof and has the core material containing a metallic element of Group 10 of the Periodic Table of Elements in a total amount of 0.1 to 3.0% by mass, thereby achieving improvement in 2nd bondability and excellent ball bondability in a high-humidity heating condition. Furthermore, a maximum concentration of Au in the skin alloy layer is preferably 15 at % to 75 at %.

A semiconductor device includes a plurality of functional element chips, an electric connection member joined to two of the functional element chips, a first wire and a resin configured to cover the functional element chips, the electric connection member and the first wire. One of the two functional element chips may be a first semiconductor chip having first and second major surface electrodes facing toward the same direction and a first rear surface electrode facing in a direction opposite to a direction in which the first major surface electrode faces. The electric connection member may be joined to the first major surface electrode. The first wire may be joined to the second major surface electrode. The first wire may include a portion overlapping with the electric connection member in a thickness direction of the first semiconductor chip.