Provided are an optical module and an optical transceiver using an optical system-in-package (O-SIP) including a photonic integrated circuit (IC), an electronic IC, and the like, in a package. The optical module includes: an optical system-in-package (O-SIP) for generating an optical signal or receiving an optical signal, in which a photonic integrated circuit (IC) and an electronic IC for driving or interfacing the photonic IC are molded inside a mold body having a first surface and a second surface which are flat, on a lower portion and an upper portion of the mold body, respectively; and a vertical coupler mounted on an upper portion of the O-SIP and having a through hole corresponding to a light entrance/exit part of the photonic IC inside the mold body, wherein an optical fiber is coupled to the through hole.

A semiconductor package includes a lower redistribution layer disposed on a lower surface of the semiconductor chip including an insulating layer, a redistribution pattern, a via, an under bump metal (UBM), and a post disposed on the redistribution pattern. The post vertically overlaps with the UBM. A mold layer is on the lower redistribution layer and surrounds the semiconductor chip. A connecting terminal is connected to the UBM. The UBM includes a first section contacting the redistribution pattern, and a second section contacting the insulating layer. The post has a ring shape having an inner surface and an outer surface when viewed in a top view. A maximum width of the inner surface is less than a maximum width of an upper surface of the first section. A maximum width of the outer surface is greater than the maximum width of the upper surface of the first section.

A fan-out package having a main die and a dummy die side-by-side is provided. A molding material is formed along sidewalls of the main die and the dummy die, and a redistribution layer having a plurality of vias and conductive lines is positioned over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die.

A semiconductor package includes: a first redistribution layer; a first semiconductor chip including a first side and a second side, wherein the first side faces the first redistribution layer; a first sealing material covering the second side of the first semiconductor chip and having a first filler content; a second sealing material formed on the first sealing material and having a second filler content lower than the first filler content; and a second redistribution layer disposed on the second sealing material.

Methods, systems, and devices for reconstructed semiconductor die evaluation and power delivery are described. A semiconductor device may be formed based on reconstructed wafers of operable dies and may support improved architectures for power delivery. In some examples, a first side of an interface block may be bonded with one or more volatile memory stacks. An evaluation procedure may be performed by probing one or more conductive pads in a second side of the interface block. The second side of the interface block may then be bonded to a first side of a host chip, and the host chip may be operable to control one or more functions of the interface block and the one or more volatile memory stacks. In some examples, a redistribution layer may be formed above a second side of the host chip to provide a power interface for the semiconductor device.

A semiconductor package is provided. The semiconductor package includes a redistribution structure having a front surface and a rear surface opposite the front surface, the redistribution structure including an insulating layer and a redistribution conductor provided in the insulating layer; a semiconductor chip provided on the rear surface and including a connection pad electrically connected to the redistribution conductor; an encapsulant provided on at least a portion of the semiconductor chip; under-bump metal (UBM) vias extending from the redistribution conductor to the front surface of the redistribution structure within the insulating layer; UBM pads provided on the front surface of the redistribution structure to correspond to the UBM vias, respectively, and each UBM pad of the UBM pads having an exposed surface convexly protruding away from the front surface of the redistribution structure; and a metal bump provided on the UBM pads and contacting the exposed surface of each UBM pad of the UBM pads.

A fan-out package having a main die and a dummy die side-by-side is provided. A molding material is formed along sidewalls of the main die and the dummy die, and a redistribution layer having a plurality of vias and conductive lines is positioned over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die.

An IC package includes one or more microelectronic devices, a plurality of package bumps disposed at a first side, and a metal structure electrically connecting at least a first device contact pad of a first microelectronic device and at least a first package bump of the plurality of package bumps. The metal structure includes an RDL trace extending between a first region aligned with the first device contact pad and a second region aligned with the first package bump, wherein the first package bump is mechanically and electrically connected directly to the second region of the RDL trace. The metal structure further includes a first via extending between the first region of the RDL trace and the first device contact pad and further includes a set of one or more support studs extending from the second region to a support surface facing the first side.