A semiconductor device includes an array of flexible connectors configured to mitigate thermomechanical stresses. In one embodiment, a semiconductor assembly includes a substrate coupled to an array of flexible connectors. Each flexible connector can be transformed between a resting configuration and a loaded configuration. Each flexible connector includes a conductive wire electrically coupled to the substrate and a support material at least partially surrounding the conductive wire. The conductive wire has a first shape when the flexible connector is in the resting configuration and a second, different shape when the flexible connector is in the loaded configuration. The first shape includes at least two apices spaced apart from each other in a vertical dimension by a first distance, and the second shape includes the two apices spaced apart from each other in the vertical dimension by a second distance different than the first distance.

A device for producing semiconductor bump metal layer includes a front end transfer module including a normal pressure transfer chamber, a base material carrier, a heating and carrying interlock vacuum chamber, and a cooling interlock vacuum chamber; a pre-cooking device for receiving the plurality of base materials, forming high vacuum, and baking the base materials; a rear end cleaning sputtering module for receiving the plurality of base materials and cleaning the plurality of base materials and sputtering metal layers; then the plurality of base materials being transferred to the cooling interlock vacuum chamber. The robot in the normal pressure transfer chamber transfers the base materials to the pre-cooking device so as to bake the base materials in high vacuum to remove vapors in the plurality of base materials; then the base materials are transferred to the heating and carrying interlock vacuum chamber for baking again to a predetermined level.

A plating system comprising a plating tank for applying plate processing to a substrate, a sensor configured to measure actual plating film thickness of the substrate, and a controller configured to control plating current supplied to the plating tank and plating time for the plate processing of the substrate within the plating tank. The controller is capable of setting target plating film thickness, plating current, and plating time as a plate processing recipe. At least one of the plating current and the plating time is automatically corrected so that the actual plating film thickness and the target plating film thickness become equal to each other, and the result is reflected in the plate processing for the subsequent substrate.

A semiconductor-mounted product includes a semiconductor package, a wiring substrate, four or more soldered portions, and a resin-reinforced portion. Each of the soldered portions electrically connects the semiconductor package to the wiring of the wiring substrate. The resin-reinforced portion is formed on a side surface of each of the soldered portions. Each of the soldered portions has a first solder region formed closer to the semiconductor package than the wiring substrate and a second solder region formed closer to the wiring substrate than the semiconductor package. A proportion of a void present in a polygon connecting centers of soldered portions located at outermost positions among the soldered portions to a sum of the void and the resin-reinforced portion is from 10% to 99%, inclusive.

Methods of reflowing electrically conductive elements on a wafer may involve directing a laser beam toward a region of a surface of a wafer supported on a film of a film frame to reflow at least one electrically conductive element on the surface of the wafer. In some embodiments, the wafer may be detached from a carrier substrate and be secured to the film frame before laser reflow. Apparatus for performing the methods, and methods of repairing previously reflowed conductive elements on a wafer are also disclosed.

A semiconductor fabrication apparatus has a transfer plate having a plurality of transfer pins to transfer a flux onto a plurality of lands on a semiconductor substrate, a holder movable with the transfer plate, to hold the transfer plate, a positioning mechanism to perform positioning of the holder so that the plurality of lands and the respective transfer pins contact each other; and a pitch adjuster to adjust a pitch of at least part of the plurality of transfer pins.

Methods of reflowing electrically conductive elements on a wafer may involve directing a laser beam toward a region of a surface of a wafer supported on a film of a film frame to reflow at least one electrically conductive element on the surface of the wafer. In some embodiments, the wafer may be detached from a carrier substrate and be secured to the film frame before laser reflow. Apparatus for performing the methods, and methods of repairing previously reflowed conductive elements on a wafer are also disclosed.

A micronozzle assembly, comprising a reservoir, an array of structures comprising micronozzles, a porous structure positioned between the reservoir and the array, and an electrode within the reservoir, wherein the electrode comprises any of a mesh, a frame along the perimeter of the cavity of the reservoir, or a rod extending into a cavity of the reservoir.

There is provided a bonding method capable of accurately positioning a bonding stage. According to an aspect of the present invention, a bonding method using a bonding apparatus including a rotation drive mechanism for rotating a bonding stage 1 about a -axis includes the steps of: (e) locking the bonding stage with respect to the -axis, and bonding a wire or bump onto a certain area of a substrate held on the bonding stage; (f) unlocking the bonding stage with respect to the -axis, and rotating the bonding stage about the -axis with the rotation drive mechanism; and (g) locking the bonding stage with respect to the -axis, and bonding a wire or bump onto a remaining region of the substrate.

A 3D integrated structure and a method for fabricating the structure. In the method, a first trimming process is performed in a peripheral region of a wafer stack to form a chamfered surface adjacent to and surrounding an active device region. As a result, a thickness of the wafer stack along the chamfered surface gradually decreases from an edge of the active device region outward. In this way, a photoresist layer can be subsequently easily applied to cover the junction of the active device region and the chamfered surface, without the formation of discontinuities there, which may affect the subsequent processes. Additionally, in the method, a second trimming process is performed at an edge of the peripheral region to form a clamping surface adjacent to and surrounding the chamfered surface. In this way, it is unnecessary to clamp the wafer stack at a top surface thereof.