A method for bonding a first substrate to a second substrate, the first substrate including, prior to bonding, a support layer, the method including removing the support layer to free a first surface substrate, thereby forming an elastic nanotopology on the first surface; stripping the first surface with rare gas atoms or depositing a thin film of metal or semiconductor onto the first surface; thermocompression bonding the first substrate to the second substrate, the contact between the first substrate and the second substrate being made at the first surface and a second surface of the second substrate, this bonding being carried out using an atomic diffusion bonding technique or a surface activation bonding technique. The stripping or deposition and the bonding step are performed under ultra-high vacuum. The pressure is between 1 and 100 kN and the temperature is between 200° C. and 600° C. in the thermocompression bonding.

Connection pads are formed in interlayer films provided respectively in interconnection layers of a sensor substrate on which a sensor surface having pixels is formed and a signal processing substrate configured to perform signal processing on the sensor substrate to make an electrical connection between the sensor substrate and the signal processing substrate. Then, a metal oxide film is formed between the interlayer films of the sensor substrate and the signal processing substrate, between the connection pad formed on a side toward the sensor substrate and the interlayer film on a side toward the signal processing substrate, and between the connection pad formed on the side toward the signal processing substrate and the interlayer film on the side toward the sensor substrate. The present technology can be applied to a laminated-type CMOS image sensor, for example.

Embodiments relate to using nanoporous metal tips to establish connections between a first body and a second body. The first body is positioned relative to the second body to align contacts protruding from a first surface of the first body with electrodes protruding from a second surface of the second body. The second surface faces the first surface. The contacts, the electrodes, or both comprise nanoporous metal tips. A relative movement is made between the first body and the second body after positioning the first body to approach the first body to the second body. The contacts and the electrodes are bonded by melting and solidifying the nanoporous metal tips after approaching the first body and the second body.

A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.

The present application provides a method for manufacturing a semiconductor package with air gaps for reducing capacitive coupling between conductive features. The method comprises: providing a first substrate with an integrated circuit; forming a first stack of insulating layers with first protruding portions on the integrated circuit; removing a topmost insulating layer in the first stack of insulating layers; forming through holes in the first stack to form a first semiconductor structure; providing a second substrate with an integrated circuit; forming a second stack of insulating layers with second protruding portions on the integrated circuit; forming a recess portion in the first stack to form a second semiconductor structure; and bonding the first semiconductor structure with the second semiconductor structure, with an air gap formed from the recess portion.

Embodiments of various systems, methods, and devices for gang flipping and individual picking dies are disclosed. The embodiments disclosed herein may be used, for example, in the manufacture of directly bonded devices.

Techniques disclosed herein relate to devices that each include one or more photonic integrated circuits and/or one or more electronic integrated circuits. In one embodiment, a device includes a silicon substrate, a die stack bonded (e.g., fusion-bonded) on the silicon substrate, and a printed circuit board (PCB) bonded on the silicon substrate, where the PCB is electrically coupled to the die stack. The die stack includes a photonic integrated circuit (PIC) that includes a photonic integrated circuit, and an electronic integrated circuit (EIC) die that includes an electronic integrated circuit, where the EIC die and the PIC die are bonded face-to-face (e.g., by fusion bonding or hybrid bonding) such that the photonic integrated circuit and the electronic integrated circuit face each other. In some embodiments, the device also includes a plurality of optical fibers coupled to the photonic integrated circuit.

A three-dimensional (3D) memory device includes a core array region and a staircase region adjacent to the core array region. The core array region includes a memory stack having a plurality of conductor layers and a plurality of dielectric layers stacked alternatingly, a first semiconductor layer disposed over the memory stack, and a channel structure extending through the memory stack and the first semiconductor layer. The staircase region includes a staircase structure, a supporting structure disposed over the staircase structure, and a plurality of contacts contacting the plurality of conductor layers in the staircase structure. The first semiconductor layer overlaps the core array region in a plan view of the 3D memory device and the supporting structure overlaps the staircase region in the plan view of the 3D memory device.

A bonding apparatus includes a first holder configured to hold a first substrate divided into multiple chips with a tape and a ring frame therebetween, the first substrate being attached to the tape, and an edge of the tape being attached to the ring frame; a second holder configured to hold a second substrate, which is disposed on an opposite side to the tape with respect to the first substrate therebetween, while maintaining a distance from the first substrate; and a pressing device configured to press the multiple chips one by one with the tape therebetween to press and bond the corresponding chip to the second substrate.

A bonding apparatus includes a first holder configured to hold a first substrate divided into multiple chips with a tape and a ring frame therebetween, the first substrate being attached to the tape, and an edge of the tape being attached to the ring frame; a second holder configured to hold a second substrate, which is disposed on an opposite side to the tape with respect to the first substrate therebetween, while maintaining a distance from the first substrate; and a pressing device configured to press the multiple chips one by one with the tape therebetween to press and bond the corresponding chip to the second substrate.