A method for forming a multilayer conductive structure includes forming a first conductive portion; forming a second conductive portion containing ruthenium (Ru) therein on the first conductive portion; forming a third conductive portion on the second conductive portion; and performing a silicidation process on the second conductive portion.

The present application discloses a method for fabricating a semiconductor device. The method includes providing a first semiconductor structure; and forming a first connecting structure comprising a first connecting insulating layer on the first semiconductor structure, two first conductive layers in the first connecting insulating layer, and a first porous layer between the two first conductive layers; wherein a porosity of the first porous layer is between about 25% and about 100%.

A structure of semiconductor device is provided, including a first circuit structure, formed on a first substrate. A first test pad is disposed on the first substrate. A second circuit structure is formed on a second substrate. A second test pad is disposed on the second substrate. A first bonding pad of the first circuit structure is bonded to a second bonding pad of the second circuit structure. One of the first test pad and the second test pad is an inner pad while another one of the first test pad and the second test pad is an outer pad, wherein the outer pad surrounds the inner pad.

A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first semiconductor device, a second semiconductor device, and an alignment material. The first semiconductor device has a first bonding layer, and the first bonding layer includes a first bond pad contacting an organic dielectric material. The second semiconductor device has a second bonding layer, and the second bonding layer includes a second bond pad contacting the organic dielectric material. The alignment material is between the first bonding layer and the second bonding layer.

In an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first Young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus.

Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or “dishing” of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. The interconnect devices are wet etched with a selective etchant, according to a formulary, for a preselected period of time or until the interconnect devices have a preselected height relative to the surface of the substrate. The formulary includes one or more oxidizing agents, one or more organic acids, and glycerol, where the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary and the glycerol is less than 10% of the formulary.

The present technology relates to a semiconductor device in which a MIM capacitive element can be formed without any process damage, and a method for manufacturing the semiconductor device. In a semiconductor device, wiring layers of a first multilayer wiring layer formed on a first semiconductor substrate and a second multilayer wiring layer formed on a second semiconductor substrate are bonded to each other by wafer bonding. The semiconductor device includes a capacitive element including an upper electrode, a lower electrode, and a capacitive insulating film between the upper electrode and the lower electrode. One electrode of the upper electrode and the lower electrode is formed with a first conductive layer of the first multilayer wiring layer and a second conductive layer of the second multilayer wiring layer. The present technology can be applied to a semiconductor device or the like formed by joining two semiconductor substrates, for example.

Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.

In one embodiment, a semiconductor device includes a first chip including a substrate, a first plug on the substrate, and a first pad on the first plug, and a second chip including a second plug and a second pad under the second plug. The second chip includes an electrode layer electrically connected to the second plug, a charge storage layer provided on a side face of the electrode layer via a first insulator, and a semiconductor layer provided on a side face of the charge storage layer via a second insulator. The first and second pads are bonded with each other, and the first and second plugs are disposed so that at least a portion of the first plug and at least a portion of the second plug do not overlap with each other in a first direction that is perpendicular to a surface of the substrate.

Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is provided. The method includes the following operations. In a first semiconductor structure, a first bonding layer is formed having a first dielectric layer and a plurality of protruding contact structures. In a second semiconductor structure, a second bonding layer is formed having a second dielectric layer and a plurality of recess contact structures. The plurality of protruding contact structures are bonded with the plurality of recess contact structures such that each of the plurality of protruding contacts is in contact with a respective recess contact structure.