A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first semiconductor structure and a second semiconductor structure that are on the first semiconductor chip and spaced apart from each other across the second semiconductor chip, and a resin-containing member between the second semiconductor chip and the first semiconductor structure and between the second semiconductor chip and the second semiconductor structure. The semiconductor package may be fabricated at a wafer level.

Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same. In some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. A first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. A plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. A first through substrate via (TSV) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first TSV to the first and second trench capacitors. The first and second trench capacitors and the electrical coupling therebetween collectively define the 3D trench capacitor.

Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.

Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.

A die bonding method with corner or side contact without impact force includes the steps: picking up a die by a die bonding device, wherein a surface of the die has no solder and bump; moving the die to one side of a die placement area of a substrate, wherein the substrate has no solder and bump; blowing one corner or one side of the die a positive pressure from the die bonding device to bend the corner/side to contact the die placement area; forming a bonding wave after the corner/side of the die contacting the die placement area, and spreading the bonding wave from the corner/side to opposite corner/side of the die, and separating the die from the die bonding device gradually and bonding the die on the die placement area; and bonding the die on the die placement area completely.

A die bonding method with corner or side contact without impact force includes the steps: picking up a die by a die bonding device, wherein a surface of the die has no solder and bump; moving the die to one side of a die placement area of a substrate, wherein the substrate has no solder and bump; blowing one corner or one side of the die a positive pressure from the die bonding device to bend the corner/side to contact the die placement area; forming a bonding wave after the corner/side of the die contacting the die placement area, and spreading the bonding wave from the corner/side to opposite corner/side of the die, and separating the die from the die bonding device gradually and bonding the die on the die placement area; and bonding the die on the die placement area completely.

A semiconductor device according to an embodiment includes a first substrate including a first insulating layer, a first conductive layer provided in the first insulating layer, a first metal layer provided in the first insulating layer, and a second metal layer provided between the first metal layer and the first conductive layer, a linear expansion coefficient of the second metal layer being higher than that of the first metal layer; and a second substrate including a second insulating layer, and a third metal layer provided in the second insulating layer, in contact with the first metal layer. The second substrate contacts with the first substrate.

A semiconductor device according to an embodiment includes a first substrate including a first insulating layer, a first conductive layer provided in the first insulating layer, a first metal layer provided in the first insulating layer, and a second metal layer provided between the first metal layer and the first conductive layer, a linear expansion coefficient of the second metal layer being higher than that of the first metal layer; and a second substrate including a second insulating layer, and a third metal layer provided in the second insulating layer, in contact with the first metal layer. The second substrate contacts with the first substrate.

Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a bonded structure includes a first bonding layer including a first bonding contact and a first bonding alignment mark, a second bonding layer including a second bonding contact and a second bonding alignment mark, and a bonding interface between the first bonding layer and the second bonding layer. The first bonding alignment mark is aligned with the second bonding alignment mark at the bonding interface, such that the first bonding contact is aligned with the second bonding contact at the bonding interface. The first bonding alignment mark includes a plurality of first repetitive patterns. The second bonding alignment mark includes a plurality of second repetitive patterns different from the plurality of first repetitive patterns.

Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a bonded structure includes a first bonding layer including a first bonding contact and a first bonding alignment mark, a second bonding layer including a second bonding contact and a second bonding alignment mark, and a bonding interface between the first bonding layer and the second bonding layer. The first bonding alignment mark is aligned with the second bonding alignment mark at the bonding interface, such that the first bonding contact is aligned with the second bonding contact at the bonding interface. The first bonding alignment mark includes a plurality of first repetitive patterns. The second bonding alignment mark includes a plurality of second repetitive patterns different from the plurality of first repetitive patterns.