Discussed is a display apparatus, including at least one horizontal semiconductor light emitting device having a first conductive electrode and a second conductive electrode; first and second wirings spaced apart from each other on a substrate, and electrically connected to the first and second conductive electrodes, respectively; a first bump disposed between the first wiring and the first conductive electrode; and a second bump disposed between the second wiring and the second conductive electrode, wherein at least one of the first and second bumps protrudes toward the other one from an edge of either one of the first and second wirings.

An array of through-silicon via (TSV) structures is formed through a silicon substrate, and package-side metal pads are formed on backside surfaces of the array of TSV structures. The silicon substrate is disposed over a carrier substrate, and an encapsulant interposer frame, such as an epoxy molding compound (EMC) interposer frame is formed around the silicon substrate. A die-side redistribution structure is formed over the silicon substrate and the EMC interposer frame, and at least one semiconductor die is attached to the die-side redistribution structure. The carrier substrate is removed from underneath the package-side metal pads. A package-side redistribution structure is formed on the package-side metal pads and on the EMC interposer frame. Overlay tolerance between the package-side redistribution wiring interconnects and the package-side metal pads increases due to increased areas of the package-side metal pads.

A semiconductor package includes a redistribution substrate, and a semiconductor chip disposed on a top surface of the redistribution substrate. The redistribution substrate includes under bump patterns laterally spaced apart from each other, a dummy pattern disposed between the under bump patterns, a passivation pattern disposed on a bottom surface of the dummy pattern, an insulating layer covering top surfaces and sidewalls of the under bump patterns and a sidewall and a top surface of the dummy pattern, and a redistribution pattern disposed on one of the under bump patterns and electrically connected to the one under bump pattern. The passivation pattern includes a different material from that of the insulating layer.

Magnetic structures may be incorporated into integrated circuit assemblies, which will enable local heating and reflow of solder interconnects for the attachment of integrated circuit devices to electronic substrates. Such magnetic structures will eliminate exposure of the entire integrated circuit assembly to elevated temperatures for an extended period of time, which eliminates associated warpage and thermal degradation consequences from such exposure. Additionally, such magnetic structures will allow for re-workability of specific solder interconnects.

A semiconductor package includes: a first semiconductor chip including a first surface and a second surface opposite to each other and including first through electrodes; at least a second semiconductor chip stacked on the first surface of the first semiconductor chip and comprising second through electrodes electrically connected to the first through electrodes; and a molding layer contacting the first surface of the first semiconductor chip and a side wall of the at least one second semiconductor chip and including a first external side wall connected to and on the same plane as a side wall of the first semiconductor chip, wherein the first external side wall of the molding layer extends to be inclined with respect to a first direction orthogonal to the first surface of the first semiconductor chip, and both the external first side wall of the molding layer and the side wall of the first semiconductor chip have a first slope that is the same for both the first external side wall of the molding layer and the side wall of the first semiconductor chip.

A semiconductor packaging method, a semiconductor assembly and an electronic device are disclosed herein. The semiconductor packaging method comprises providing at least one semiconductor device and a first carrier board. The at least one semiconductor device has a passive surface with first alignment solder parts formed thereon, and the first carrier board has a plurality of corresponding second alignment solder parts formed thereon. The method further comprises forming alignment solder joints by aligning and soldering the first alignment solder parts to respective ones of the second alignment solder parts; removing the first carrier board after attaching a second carrier board to the active surface of the at least one semiconductor device; forming a molded package body on one side of the second carrier board to encapsulate the at least one semiconductor device; and removing the second carrier board to expose the connecting terminals.

A method for forming a chip package is provided. The method includes forming a plurality of conductive structures over a carrier substrate. The method also includes disposing a semiconductor die over the carrier substrate such that the conductive ti structures surround the semiconductor die. The method further includes disposing a shielding element over the semiconductor die and the conductive structures. The shielding element is electrically connected to the conductive structures.

Provided is a semiconductor package including: at least one semiconductor device on a first substrate; a non-conductive film (NCF) on the at least one semiconductor device and comprising an irreversible thermochromic pigment; and a molding member on the at least one semiconductor device in a lateral direction, wherein a content of the irreversible thermochromic pigment in the NCF is about 0.1 wt % to about 5 wt % with respect to a weight of the NCF.

A package structure and method of manufacturing is provided, whereby heat dissipating features are provided for heat dissipation. Heat dissipating features include conductive vias formed in a die stack, thermal chips, and thermal metal bulk, which can be bonded to a wafer level device. Hybrid bonding including chip to chip, chip to wafer, and wafer to wafer provides thermal conductivity without having to traverse a bonding material, such as a eutectic material. Plasma dicing the package structure can provide a smooth sidewall profile for interfacing with a thermal interface material.

A display module is provided. The display module includes: a substrate; a thin film transistor (TFT) layer formed on one surface of the substrate; and a plurality of micro LEDs disposed on the TFT layer. The plurality of micro LEDs are transferred from a transfer substrate to the TFT layer by a laser beam radiated to the transfer substrate through openings of a mask. The openings correspond to regions in which the respective micro LEDs of the transfer substrate are arranged and the openings correspond to a width, a length, or a unit area of each of the micro LEDs.