Patent classifications
H01L2224/81007
Method of forming an electronic device structure having an electronic component with an on-edge orientation and related structures
A method of forming an electronic device structure includes providing an electronic component having a first major surface, an opposing second major surface, a first edge surface, and an opposing second edge surface. A substrate having a substrate first major surface and an opposing substrate second major surface is provided. The second major surface of the first electronic component is placed proximate to the substrate first major surface and providing a conductive material adjacent the first edge surface of the first electronic component. The conductive material is exposed to an elevated temperature to reflow the conductive material to raise the first electronic component into an upright position such that the second edge surface is spaced further away from the substrate first major surface than the first edge surface. The method is suitable for providing electronic components, such as antenna, sensors, or optical devices in a vertical or on-edge.
Semiconductor device and semiconductor device manufacturing method
A semiconductor device includes a substrate that includes a first insulating layer, a conductive layer on the first insulating layer, a second insulating layer on the conductive layer, and an opening that passes through the conductive layer and the second insulating layer and in which part of the conductive layer is exposed, a conductive material that contacts at least the first insulating layer and the part of the conductive layer in the opening, and a semiconductor chip that has an electrode extending towards the first insulating layer within the opening and contacting the conductive material.
Metal-bump sidewall protection
A method includes forming a metal bump on a top surface of a first package component, forming a solder region on a top surface of the metal bump, forming a protection layer extending on a sidewall of the metal bump, reflowing the solder region to bond the first package component to a second package component, and dispensing an underfill between the first package component and the second package component. The underfill is in contact with the protection layer.
Bonding interposer and integrated circuit chip, and ultrasound probe using the same
The method of bonding an interposer and an integrated circuit chip includes preparing an interposer including an insulator and conductive lines each having one end exposed to a first surface of the insulator and another end exposed to a second surface opposite to the first surface; placing a bonding mask on the interposer; forming through-holes on the bonding mask before or after the placing of the bonding mask on the interposer; filling the plurality with a conductive material; and bonding an integrated circuit chip to the bonding mask.
Semiconductor packages including an anchor structure
A semiconductor package includes a package substrate and a semiconductor chip mounted on the package substrate. The package substrate includes a signal bump land and an anchoring bump land, and the semiconductor chip includes a signal bump and an anchoring bump. The signal bump is bonded to the signal bump land, the anchoring bump is disposed to be adjacent to the anchoring bump land, and a bottom surface of the anchoring bump is located at a level which is lower than a top surface of the anchoring bump land with respect to a surface of the package substrate.
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device includes arranging a mask on a support. The mask includes a first area and a second area. A substrate is arranged on the mask. The substrate has a mounting area and a non-mounting area. A solder paste is applied on the mounting area of the substrate. After applying the solder paste, at least one electronic device is arranged on the mounting area. A light soldering process is performed by emitting light on the substrate from a light source above the substrate. The first area of the mask is positioned under the non-mounting area and the second area of the mask is positioned under the mounting area.
SEMICONDUCTOR DIE WITH SOLDER RESTRAINING WALL
A semiconductor die includes a semiconductor surface including circuitry electrically connected to top-level bond pads exposed on a top surface of the semiconductor die, the top-level bond pads including inner bond pads and outer bond pads positioned beyond the inner bond pads. There is solder on at least the inner bond pads. A ring structure is positioned around a location of at least the inner bond pads.
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE THEREOF
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a device includes coupling a first semiconductor device to a second semiconductor device by spacers. The first semiconductor device has first contact pads disposed thereon, and the second semiconductor device has second contact pads disposed thereon. The method includes forming an immersion interconnection between the first contact pads of the first semiconductor device and the second contact pads of the second semiconductor device.
METHOD AND SYSTEM FOR POSITIONING USING NEAR FIELD TRANSDUCERS, PARTICULARLY SUITED FOR POSITIONING ELECTRONIC CHIPS USING INTERPOSERS
Method for positioning and orienting a first object relative to a second object. Method includes positioning a near field transducer having an aperture on the first object, and directing a laser light toward the aperture of the near field transducer on the first object to create an effervescent wave on the other side of the aperture. Positioning a sensor on the second object for detecting the effervescent wave from the near field transducer. Providing an algorithm, and using information obtained from the sensor on the second object in the algorithm to control a nanopositioning system to position one of the first and second objects in a desired position and orientation relative to the other one of the first and second objects. One or both of the first and second objects may be an interposer, such as a silicon or glass interposer.
Light-emitting device package including a lead frame
A light-emitting device package includes a lead frame, a light-emitting device chip, a molding structure, and a plurality of slots. The lead frame includes a first lead and a second lead including metal and spaced apart from each other. The light-emitting device chip is mounted on a first area of the lead frame, which includes a part of the first lead and a part of the second lead. The molding structure includes an outer barrier surrounding an outside of the lead frame and an inner barrier. The plurality of slots are formed in each of the first lead and the second lead. The inner barrier divides the lead from into the first area and a second area. The inner barrier fills between the first lead in the second lead. The second area is located outside of the first area. The plurality of slots are filled by the molding structure.