A package structure and a method for manufacturing a package structure are provided. The package structure includes a first wiring structure and at least one electronic device. The at least one electronic device is connected to the first wiring structure through at least two joint structures. The at least two joint structures respectively include different materials.

A film structure, a chip carrier assembly, and a chip carrier device are provided. The film structure includes a film and a plurality of micro-heaters. In which, the film is applied on a substrate, and the plurality of micro-heaters is disposed on top of the film or in the film. The chip carrier assembly includes a circuit substrate and the film structure. In which, the circuit substrate carries a plurality of chips. The chip carrier device includes the chip carrier assembly and a suction unit. In which, the suction unit is arranged above the chip carrier assembly to attach on and transfer the plurality of chips to the circuit substrate. The chips are disposed on the circuit substrate through solder balls, and the micro-heaters heat the solder balls that are in contact with the chips.

A wafer structure, a method for manufacturing the wafer structure, and a chip structure are provided. In a case that two wafers are bonded together, an opening extending through a substrate of one of the wafers is formed at a back surface of the wafer, and a concave-convex structure is formed in the dielectric layer under the opening. At least one of concave portions of the concave-convex structure extends to expose the interconnection layer of the wafer structure. A pad is formed on the concave-convex structure by filling the concave-convex structure, and the pad has the same concave-convex arrangement as the concave-convex structure. In this way, the pad has a concave-convex surface, such that a contact surface area of the pad is effectively increased without increasing a floor space of the pad.

A module includes a substrate having a plurality of contact regions, and a spacer-chip assembly. The spacer-chip assembly in turn includes at least first and second semiconductor dies, each having a plurality of electrical interconnect pillars and a plurality of contact pads, and a spacer wafer. The at least first and second semiconductor dies are secured to the spacer wafer, and the spacer wafer includes at least first and second semiconductor circuit features coupled to a first portion of the contact pads of the at least first and second semiconductor dies. The spacer wafer includes wiring electrically coupling the at least first and second semiconductor dies via a second portion of the contact pads. The spacer wafer has a plurality of holes formed therethrough. The plurality of electrical interconnect pillars extend through the holes and are secured to the contact regions on the substrate.

An electronic device structure includes a substrate having a substrate first major surface, an opposing substrate second major surface, and a first conductive pattern adjacent to the substrate first major surface. A first electronic component is coupled to the substate and includes a first component first side and a first device structure adjacent to the first component first side. A second electronic component is adjacent to the substate second major surface and includes a second component first side and a second device structure adjacent to the second component first side. A third electronic component is coupled to the substrate. The first electronic component is generally orthogonal to the substrate and the first device structure is oriented in a first direction, and the second device structure is oriented in a second direction different than the first direction.

A semiconductor package includes a first substrate, a first flow channel and a second flow channel. The first flow channel is on the first substrate. The second flow channel is on the first substrate and in fluid communication with the first flow channel. The second flow channel is spaced from an inlet and an outlet of the first flow channel. The first flow channel and the second flow channel constitute a bonding region of the first substrate.

Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure has a first conductive layer on a first substrate and a second conductive layer on a second substrate. A bonding structure is disposed between the first conductive layer and the second conductive layer. A support structure is disposed between the first substrate and the second substrate. A passivation layer covers a bottom surface of the first conductive layer and has a lower surface facing an uppermost surface of the support structure.

A display panel comprising a display substrate having a display area and a pad area disposed around the display area. A connection wire is disposed on the pad area of the display substrate. A signal wire is disposed on the connection wire. A supporter is disposed between the display substrate and the connection wire. The connection wire directly contacts the supporter.

A semiconductor assembly packaging method, a semiconductor assembly and an electronic device are provided. The method comprises providing an interconnect board and at least one semiconductor device; aligning and attaching the at least one semiconductor device to the interconnect board by forming a plurality of alignment solder joints; applying pressure to the at least one semiconductor device and/or the interconnect board while the alignment solder joints are in a molten or partially molten state, whereby first connection terminals on the interconnect board are joined with and bonded to corresponding second connection terminals on the at least one semiconductor device. Using the packaging method, the semiconductor device and the interconnect board can be aligned accurately using relatively simple and low cost processes and equipment. The method can also be used to align and bond at least one semiconductor device to another semiconductor device.