A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.

A radial solder ball pattern is described for a printed circuit board and for a chip to be attached to the printed circuit board is described. In one example, the pattern comprises a central power connector area having a plurality of power connectors to provide power to an attached chip, a signal area having a plurality of signal connectors to communicate signals to the attached chip, an edge area surrounding the signal area and the central power connector area, and a plurality of traces each coupled to a signal connector, the traces extending from the respective coupled signal connector away from the central power connector to connect to an external component, wherein the signal connectors are placed in rows, the rows having a greater separation near the edge area than near the central area.

A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.

A method of forming a semiconductor device includes arranging a semi-finished substrate, which has been tested and is known to be good, on a carrier substrate. Encapsulating the semi-finished substrate in a first encapsulant and arranging at least one semiconductor die over the semi-finished substrate. Electrically coupling at least one semiconductor component of the at least one semiconductor die to the semi-finished substrate and encasing the at least one semiconductor die and portions of the first encapsulant in a second encapsulant. Removing the carrier substrate from the semi-finished substrate and bonding a plurality of external contacts to the semi-finished substrate.

An apparatus, comprising an integrated circuit (IC) package having at least one solder bond pad, a die having at least one solder bond pad, wherein the die is bonded to the IC package by at least one solder joint between the at least one solder bond pad of the die, and the at least one solder bond pad of the IC package, and an underfill material between the IC package and the die, wherein the at least one solder joint is embedded in the underfill material, and wherein the at least one solder joint comprises a first metallurgy and a second metallurgy.

A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.

Certain embodiments of the present disclosure provide a method for soldering a chip onto a surface. The method generally includes forming a bonding pad on the surface on which the chip is to be soldered, wherein the bonding pad is surrounded, at least in part, by dielectric material. The method may also include treating the dielectric material to render the dielectric material superomniphobic, and soldering the chip onto the bonding pad.

A power amplifier module includes a module substrate, a power transistor die, and a heat spreader. The module substrate has first, second, and third module pads exposed at a mounting surface. The power transistor die has an input/output surface that faces the mounting surface, an opposed ground surface, an input pad electrically coupled to the first module pad, an output pad electrically coupled to the second module pad, and an integrated power transistor. In an embodiment, the power transistor is a field effect transistor with a gate terminal coupled to the input pad, a drain terminal coupled to the output pad, and a source terminal coupled to the ground surface. The heat spreader has a thermal contact surface that is physically and electrically coupled to the ground surface of the power transistor die. An electrical ground contact structure is connected between the thermal contact surface and the third module pad.

A bump-on-trace (BOT) interconnection in a package and methods of making the BOT interconnection are provided. An embodiment BOT interconnection comprises a landing trace including a distal end, a conductive pillar extending at least to the distal end of the landing trace; and a solder feature electrically coupling the landing trace and the conductive pillar. In an embodiment, the conductive pillar overhangs the end surface of the landing trace. In another embodiment, the landing trace includes one or more recesses for trapping the solder feature after reflow. Therefore, a wetting area available to the solder feature is increased while permitting the bump pitch of the package to remain small.

A bump-on-trace (BOT) interconnection in a package and methods of making the BOT interconnection are provided. An embodiment BOT interconnection comprises a landing trace including a distal end, a conductive pillar extending at least to the distal end of the landing trace; and a solder feature electrically coupling the landing trace and the conductive pillar. In an embodiment, the conductive pillar overhangs the end surface of the landing trace. In another embodiment, the landing trace includes one or more recesses for trapping the solder feature after reflow. Therefore, a wetting area available to the solder feature is increased while permitting the bump pitch of the package to remain small.