H01L2224/81908

METHOD AND SYSTEM FOR POSITIONING USING NEAR FIELD TRANSDUCERS, PARTICULARLY SUITED FOR POSITIONING ELECTRONIC CHIPS USING INTERPOSERS
20170365497 · 2017-12-21 ·

Method for positioning and orienting a first object relative to a second object. Method includes positioning a near field transducer having an aperture on the first object, and directing a laser light toward the aperture of the near field transducer on the first object to create an effervescent wave on the other side of the aperture. Positioning a sensor on the second object for detecting the effervescent wave from the near field transducer. Providing an algorithm, and using information obtained from the sensor on the second object in the algorithm to control a nanopositioning system to position one of the first and second objects in a desired position and orientation relative to the other one of the first and second objects. One or both of the first and second objects may be an interposer, such as a silicon or glass interposer.

PILLARS AS STOPS FOR PRECISE CHIP-TO-CHIP SEPARATION
20230187401 · 2023-06-15 ·

A stacked device including a first substrate that includes a quantum information processing device, a second substrate bonded to the first substrate, and multiple bump bonds and at least one pillar between the first substrate and the second substrate. Each bump bond of the multiple bump bonds provides an electrical connection between the first substrate and the second substrate. At least one pillar defines a separation distance between a first surface of the first substrate and a first surface of the second substrate. A cross-sectional area of each pillar is greater than a cross-sectional area of each bump bond of the multiple bump bonds, where the cross-sectional area of each pillar and of each bump bond is defined along a plane parallel to the first surface of the first substrate or to the first surface of the second substrate.

APPARATUS FOR BONDING A SEMICONDUCTOR CHIP AND METHOD OF FORMING A SEMICONDUCTOR DEVICE
20170352642 · 2017-12-07 ·

An apparatus for bonding a semiconductor chip to a package substrate, the apparatus comprising: a die-bonding unit configured to attach the semiconductor chip to the package substrate; a load-measuring unit installed at the die-bonding unit, the load-measuring unit including a panel having a plurality of regions and a plurality of load-measuring members with at least one load-measuring member arranged in each of the regions of the panel to measure load values applied to each of the regions; and a controller configured to determine a load and a flatness of the semiconductor chip based on the load values measured by the load-measuring members.

Laser compression bonding device and method for semiconductor chip

A laser compression bonding device and method for a semiconductor chip are proposed. The device includes a conveyor unit that transports a semiconductor chip and a substrate, and a bonding head that includes a bonding tool for applying a pressure to the chip and substrate, a laser beam generator for emitting a laser beam, a thermal imaging camera for measuring temperatures of the surfaces of semiconductor chip and substrate, and a compression unit for controlling a pressure applied by the bonding tool and a position thereof, wherein the compression unit includes a mount on which the bonding tool is detachably mounted, and a servo motor and a load cell that apply a pressure to the mount or control a position thereof. The servo motor is controlled with two values for pressure application and positioning.

JOINT STRUCTURE IN SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

A semiconductor package includes first and second package components stacked upon and electrically connected to each other, and first and second joint structures. The first package component includes first and second conductive bumps, the second package component includes third and fourth conductive bumps having dimensions greater than those of the first and second conductive bumps. The first joint structure partially covers the first and third conductive bumps. The second joint structure partially covers the second and the fourth conductive bumps. A first angle between a sidewall of the first conductive bump and a tangent line at an end point of a boundary of the first joint structure on the first conductive bump is greater than a second angle between a sidewall of the second conductive bump and a tangent line at an end point of a boundary of the second joint structure on the second conductive bump.

System and method to enhance reliability in connection with arrangements including circuits

A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.

Semiconductor device and manufacturing method thereof

A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise connection verification for a first one or more mounted components prior to additional assembly.

Dual-side reinforcement flux for encapsulation

Dual-side reinforcement (DSR) materials and methods for semiconductor fabrication. The DSR materials exhibit the properties of conventional underfill materials with enhanced stability at room temperature.

Bonding corners of light emitting diode chip to substrate using laser

A light emitting diode (LED) chip is bonded to a substrate. The LED chip includes a plurality of electrodes that each corresponds to a contact on the substrate. The plurality of electrodes are exposed to one or more laser beams for coupling the LED chip to the substrate. The laser beams may be directed to one or more edges or corners of the plurality of electrodes, where the edges or corners lie outside emission areas of LEDs on the LED chip.

MODELING OF NANOPARTICLE AGGLOMERATION AND POWDER BED FORMATION IN MICROSCALE SELECTIVE LASER SINTERING SYSTEMS
20170282247 · 2017-10-05 ·

Exemplified microscale selective laser sintering (μ-SLS or micro-SLS) systems and methods facilitate modeling of the nanoparticle powder bed by simulating the interactions between particles during the powder spreading operation. In particular, the exemplified methods and system use multiscale modeling techniques to accurately predict the formation and mechanical/electrical properties of parts produced by selective laser sintering of powder beds. Discrete element modeling is used for nanoscale particle interactions by implementing the different forces dominant at nanoscale. A heat transfer analysis is used to predict the sintering of individual particles in the powder beds in order to build up a complete structural model of the parts that are being produced by the SLS process.