A method includes picking up a first package component, removing an oxide layer on an electrical connector of the first package component, placing the first package component on a second package component after the oxide layer is removed, and bonding the first package component to the second package component.

A semiconductor device manufacturing device (10) comprises: a stage (16) on which a substrate (100) is loaded; a bonding head (14) that is disposed facing the stage (16) and that bonds a semiconductor chip (110) to the substrate (100); and a controller (18). The bonding head (14) includes: an attachment (33) that holds the semiconductor chip (110) by suctioning; and a heating part (31) that detachably holds the attachment (33) and that heats the attachment (33). The heating part (31) has a first heating area (32a) and a second heating area (32b) that surrounds the first heating area (32a) in the horizontal direction. The controller (18) controls the temperatures of the first heating area (32a) and the second heating area (32b) independently.

The present disclosure is directed to a compact vertical oven for reflow of solder bumps for backend processes in semiconductor wafer assembly and packaging. This disclosure describes a vertical oven which uses a plurality of wafers (e.g., an example value is 50-100 wafers) in a batch with controlled injection of the reducing agent (e.g. formic acid), resulting in a process largely free of contamination. This disclosure describes controlled formic acid flow through a vertical system using laminar flow technology in a sub-atmospheric pressure environment, which is not currently available in the industry. The efficacy of the process depends on effective formic acid vapor delivery, integrated temperature control during heating and cooling, and careful design of the vapor flow path with exhaust. Zone-dependent reaction dynamics managed by vapor delivery process, two-steps temperature ramp control, and controlled cooling process and formic acid content ensures the effective reaction without any flux.

Provided is a laser reflow apparatus for reflowing electronic components on a substrate disposed on a stage, the apparatus including: a laser emission unit comprised of a plurality of laser modules for emitting a laser beam having a flat top output profile in at least one section of the substrate on which the electronic components are disposed; a camera unit comprising at least one camera module for capturing a reflowing process of the electronic components performed by the laser beam; and a laser output control unit configured to generate a control signal for independently controlling the respective laser modules of the laser emission unit based on a signal output from the camera unit and apply the control signal to the laser emission unit.

Provided is a flip-chip laser bonding system for bonding a semiconductor chip in the form of a flip chip to a substrate using a laser beam. In the flip-chip laser bonding system, the semiconductor chip is laser-bonded to the substrate while pressure is applied to the semiconductor chip. Accordingly, even a semiconductor chip that is bent or is capable of being bent can be bonded to a semiconductor chip without contact failure.

Provided is a flip-chip bonding apparatus using VCSEL device, and more particularly, to a flip-chip bonding apparatus using VCSEL device for bonding a flip-chip type semiconductor chip to a substrate using infrared laser light generated from the VCSEL device. The flip-chip bonding apparatus using VCSEL device may quickly control laser light to bond a semiconductor chip to a substrate, with high productivity and high quality.

A semiconductor manufacturing method of mounting a semiconductor chip or a stacked body of semiconductor chips on a support substrate placed on a stage, determines whether a predetermined condition is satisfied during a mounting processing of the semiconductor chip or the stacked body, evacuates, together with the support substrate, the semiconductor chip or the stacked body that has mounted on the support substrate before the determination when it is determined that the predetermined condition is satisfied, determines whether to resume the mounting processing of the semiconductor chip or the stacked body after the evacuation; and returns the evacuated semiconductor chip or the evacuated stacked body to a position before the evacuation and continuing the mounting processing when it is determined that the mounting processing is resumed.

Test structures and methods for superconducting bump bond electrical characterization are used to verify the superconductivity of bump bonds that electrically connect two superconducting integrated circuit chips fabricated using a flip-chip process, and can also ascertain the self-inductance of bump bond(s) between chips. The structures and methods leverage a behavioral property of superconducting DC SQUIDs to modulate a critical current upon injection of magnetic flux in the SQUID loop, which behavior is not present when the SQUID is not superconducting, by including bump bond(s) within the loop, which loop is split among chips. The sensitivity of the bump bond superconductivity verification is therefore effectively perfect, independent of any multi-milliohm noise floor that may exist in measurement equipment.

A stacked device including a first substrate that includes a quantum information processing device, a second substrate bonded to the first substrate, and multiple bump bonds and at least one pillar between the first substrate and the second substrate. Each bump bond of the multiple bump bonds provides an electrical connection between the first substrate and the second substrate. At least one pillar defines a separation distance between a first surface of the first substrate and a first surface of the second substrate. A cross-sectional area of each pillar is greater than a cross-sectional area of each bump bond of the multiple bump bonds, where the cross-sectional area of each pillar and of each bump bond is defined along a plane parallel to the first surface of the first substrate or to the first surface of the second substrate.

A semiconductor substrate including an upper surface and a lower surface may include a bump pad unit disposed on the upper surface. The semiconductor substrate may also include test pads disposed on the upper surface or the lower surface. The semiconductor substrate may also include traces configured to connect the bump pad unit and the test pads. The bump pad unit includes a main bump pad disposed on the upper surface, and a plurality of side bump pads disposed on the upper surface to be spaced apart from the main bump pad. The traces may connect the main bump pad and the plurality of side bump pads to the test pads in a one-to-one manner.