A method of mounting a plurality of semiconductor or microelectronic chips or dies, the method including providing a carrier, temporarily adhering the plurality of semiconductor or microelectronic chips or dies to the carrier with active faces of the chips or dies facing towards the carrier, covering backsides of the chips and filling empty spaces between the chips or dies with a metallic material to thereby define an assembly of the chips or dies and the metallic material, and releasing the assembly from the carrier, wherein each chip or die comprises at least one bonding ring higher than a height of the active face of the respective chip or die or any connections on the active face of the respective chip or die.

A method of mounting a plurality of semiconductor or microelectronic chips or dies, the method including providing a carrier, temporarily adhering the plurality of semiconductor or microelectronic chips or dies to the carrier with active faces of the chips or dies facing towards the carrier, covering backsides of the chips and filling empty spaces between the chips or dies with a metallic material to thereby define an assembly of the chips or dies and the metallic material, and releasing the assembly from the carrier, wherein each chip or die comprises at least one bonding ring higher than a height of the active face of the respective chip or die or any connections on the active face of the respective chip or die.

Electronic assemblies including substrates and their manufacture are described. One assembly includes a die embedded in a dielectric layer in a multilayer substrate, and a dielectric region embedded in the dielectric layer in the multilayer substrate. The multilayer substrate includes a die side and a land side, with the first dielectric region and the dielectric layer extending to the die side. A plurality of vias are positioned within the first dielectric region, the vias extending to pads on the die side. Other embodiments are described and claimed.

Image sensor devices, methods of manufacture thereof, and semiconductor device manufacturing methods are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes bonding a first semiconductor wafer to a second semiconductor wafer, the first semiconductor wafer comprising a substrate and an interconnect structure coupled to the substrate. The method includes removing a portion of the substrate from the first semiconductor wafer to expose a portion of the interconnect structure.

Image sensor devices, methods of manufacture thereof, and semiconductor device manufacturing methods are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes bonding a first semiconductor wafer to a second semiconductor wafer, the first semiconductor wafer comprising a substrate and an interconnect structure coupled to the substrate. The method includes removing a portion of the substrate from the first semiconductor wafer to expose a portion of the interconnect structure.

A method of and device for making a three dimensional electronic circuit. The method comprises coupling one or more magnet wires with a substrate along a surface contour of the substrate, immobilizing the one or more magnet wires on the substrate, and forming the electronic circuit by electrically coupling the one or more magnet wires with an integrated circuit chip.

A wiring substrate includes a core substrate. The core substrate includes a first surface, a second surface, and an opening extending through the core substrate between the first and second surfaces. A first conductive film is formed on the first surface and covers the opening. A second conductive film is formed on the second surface. The second conductive film covers the opening. An electronic component is arranged in the opening and connected to the first conductive film. An insulator fills the opening. A first wiring portion includes alternately stacked insulative layers and wiring layers and covers the first surface of the core substrate and the first conductive film. A second wiring portion includes alternately stacked insulative layers and wiring layers, and covers the second surface of the core substrate and the second conductive film.

A method of manufacturing a semiconductor device includes providing a first semiconductor chip comprising a first metallic structure, a first surface and a second surface opposite to the first surface; providing a second semiconductor chip comprising a second metallic structure; bonding the first semiconductor chip with the second semiconductor chip on the second surface; forming a first recessed portion including a first sidewall and a first bottom surface coplanar with a top surface of the first metallic structure; forming a second recessed portion including a second sidewall and a second bottom surface coplanar with a top surface of the second metallic structure; forming a dielectric layer over the first sidewall and the second sidewall; and forming a conductive material over the dielectric layer, the top surface of the first metallic structure and the top surface of the second metallic structure.

A method of manufacturing a semiconductor device includes providing a first semiconductor chip comprising a first metallic structure, a first surface and a second surface opposite to the first surface; providing a second semiconductor chip comprising a second metallic structure; bonding the first semiconductor chip with the second semiconductor chip on the second surface; forming a first recessed portion including a first sidewall and a first bottom surface coplanar with a top surface of the first metallic structure; forming a second recessed portion including a second sidewall and a second bottom surface coplanar with a top surface of the second metallic structure; forming a dielectric layer over the first sidewall and the second sidewall; and forming a conductive material over the dielectric layer, the top surface of the first metallic structure and the top surface of the second metallic structure.

A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.