A method for fabricating a semiconductor die package includes: providing a semiconductor transistor die, the semiconductor transistor die having a first contact pad on a first lower main face and/or a second contact pad on an upper main face; fabricating a frontside electrical conductor onto the second contact pad and a backside electrical conductor onto the first contact pad; and applying an encapsulant covering the semiconductor die and at least a portion of the electrical conductor, wherein the frontside electrical conductor and/or the backside electrical conductor is fabricated by laser-assisted structuring of a metallic structure.

A method of forming a semiconductor structure on a wafer includes depositing a polymer layer on the wafer in a wafer-level packaging process, forming at least one wafer-level packaging structure in the polymer layer using a direct writing process that alters a chemical property of portions of the polymer layer that have been directly written to, and removing portions of the polymer layer that have not been written to by the direct writing process revealing the at least one wafer-level packaging structure. In some embodiments, the direct writing process is a two-photon polymerization process that uses a femtosecond laser in combination with a pair of galvanometric laser scanners to solidify portions of the polymer layer to form the wafer-level packaging structure.

A method of forming a semiconductor structure on a wafer includes depositing a polymer layer on the wafer in a wafer-level packaging process, forming at least one wafer-level packaging structure in the polymer layer using a direct writing process that alters a chemical property of portions of the polymer layer that have been directly written to, and removing portions of the polymer layer that have not been written to by the direct writing process revealing the at least one wafer-level packaging structure. In some embodiments, the direct writing process is a two-photon polymerization process that uses a femtosecond laser in combination with a pair of galvanometric laser scanners to solidify portions of the polymer layer to form the wafer-level packaging structure.

Package structures and methods are provided for constructing multi-chip package structures using semiconductor wafer-level-fan-out techniques in conjunction with back-end-of-line fabrication methods to integrate different size chips (e.g., different thicknesses) into a planar package structure. The packaging techniques take into account intra-chip thickness variations and inter-chip thickness differences, and utilize standard back-end-of-line fabrication methods and materials to account for such thickness variations and differences. In addition, the back-end-of-line techniques allow for the formation of multiple layers of wiring and inter-layer vias which provide high density chip-to-chip interconnect wiring for high-bandwidth I/O communication between the package chips, as well as redistribution layers to route power/ground connections between active-side connections of the semiconductor chips to an area array of solder bump interconnects on a bottom side of the multi-chip package structure.

Package structures and methods are provided for constructing multi-chip package structures using semiconductor wafer-level-fan-out techniques in conjunction with back-end-of-line fabrication methods to integrate different size chips (e.g., different thicknesses) into a planar package structure. The packaging techniques take into account intra-chip thickness variations and inter-chip thickness differences, and utilize standard back-end-of-line fabrication methods and materials to account for such thickness variations and differences. In addition, the back-end-of-line techniques allow for the formation of multiple layers of wiring and inter-layer vias which provide high density chip-to-chip interconnect wiring for high-bandwidth I/O communication between the package chips, as well as redistribution layers to route power/ground connections between active-side connections of the semiconductor chips to an area array of solder bump interconnects on a bottom side of the multi-chip package structure.

A semiconductor package includes a chip, a redistribution structure, and first under-ball metallurgies patterns. The chip includes conductive posts exposed at an active surface. The redistribution structure is disposed on the active surface. The redistribution structure includes a first dielectric layer, a topmost metallization layer, and a second dielectric layer. The first dielectric layer includes first openings exposing the conductive posts of the chip. The topmost metallization layer is disposed over the first dielectric layer and is electrically connected to the conductive posts. The topmost metallization layer comprises first contact pads and routing traces connected to the first contact pads. The second dielectric layer is disposed on the topmost metallization layer and includes second openings exposing the first contact pads. The first under-ball metallurgies patterns are disposed on the first contact pads, extending on and contacting sidewalls and top surfaces of the first contact pads.

A semiconductor device package includes a substrate and an electronic component disposed on the substrate. The electronic component has an active surface facing away from the substrate. The substrate has a first conductive pad and a second conductive pad disposed thereon. The electronic component has a first electrical contact and a second electrical contact disposed on the active surface. The semiconductor device package further includes a first metal layer connecting the first electrical contact with the first conductive pad, a second metal layer connecting the second electrical contact with the second conductive pad, a first seed layer disposed below the first metal layer; and a first isolation layer disposed between the first metal layer and the second metal layer. A method of manufacturing a semiconductor device package is also disclosed.

A method for producing an electric circuit in which a contact carrier comprising a first contact area and a second contact area is provided. An insulating body is applied to the circuit carrier and at least partially covers the first contact area and the second contact area. The insulating body comprises cut-outs in regions both contact areas. A flowable electrical conducting medium is introduced into the insulating body.

A method for producing electronic devices includes fixing a die that includes an electronic component with integral contacts to a dielectric substrate. After fixing the die, a conductive trace is printed over both the dielectric substrate and at least one of the integral contacts, so as to create an ohmic connection between the conductive trace on the substrate and the electronic component.

A method for producing electronic devices includes fixing a die that includes an electronic component with integral contacts to a dielectric substrate. After fixing the die, a conductive trace is printed over both the dielectric substrate and at least one of the integral contacts, so as to create an ohmic connection between the conductive trace on the substrate and the electronic component.