A method including stacking a number of silicon dice such that one or more edges of the dice are in vertical alignment, where the one or more edges include a number of connection pads. The method also includes positioning a connecting wire on a substantially perpendicular axis to the one or more edges. The connecting wire includes a number of solder blocks formed thereon. The solder blocks are spaced at intervals associated with a distance between a first set of aligned connection pads on the dice. The connecting wire is positioned such that the solder blocks are in contact with the first set of aligned connection pads. The method also includes applying heat to cause the solder blocks to reflow and physically and electrically couple the connecting wire to the connection pads.

A method for inserting a wire into a longitudinal groove of a semiconductor chip for the assembly thereof, the groove containing a pad made of a bonding material having a set melting point, comprises: in a positioning step, placing a longitudinal section of the wire along the groove, in forced abutment against the pad; and, in an insertion step, exposing a zone containing at least one portion of the pad to a processing temperature higher than the melting point of the bonding material and for a sufficient time to make the pad at least partially melt, and causing the wire to be inserted into the groove. The present disclosure also relates to a piece of equipment allowing the insertion method to be implemented.

A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, an electronic component, a bonding wire, and a supporter. The electronic component is disposed on the substrate. The bonding wire includes a first terminal connected to the electronic component and a second terminal connected to the substrate. The bonding wire is disposed against the supporter.

In a described example, an apparatus includes a package substrate with a split die pad having a slot between a die mount portion and a wire bonding portion; a first end of the wire bonding portion coupled to the die mount portion at one end of the slot; a second end of the wire bonding portion coupled to a first lead on the package substrate. At least one semiconductor die is mounted on the die mount portion; a first end of a first wire bond is bonded to a first bond pad on the at least one semiconductor die; a second end of the first wire bond is bonded to the wire bonding portion; and mold compound covers the at least one semiconductor die, the die mount portion, the wire bonding portion, and fills the slot.

A system includes a substrate; a bond pad; a wire spanning above the substrate, having a first end bonded to the bond pad and a second end extending from the bond pad to terminate in a second end thereof; and a support structure disposed on the substrate, the support structure comprising at least a side wall and extending from the substrate to terminate in an end portion spaced from the substrate to support the wire.

One aspect relates to a method of manufacture of an electronic assembly comprising at least these steps: providing a substrate having at least a first contact area; positioning a spot of a UV curable substance on the substrate; positioning an electrically conductive item on the substrate wherein the electrically conductive item is superimposed on the first contact area and on the spot of curable substance; exposing the UV curable substance to UV irradiation, wherein a mechanical connection between the electrically conductive item and substrate is formed; and optionally connecting the first contact area with the electrically conductive item. One aspect relates to an electronic assembly comprising a substrate with a contact area, a spot of a cured substance on the substrate and an electrically conductive item that is in electrically conductive connection with the first contact area and mechanically connected through the spot of cured substance to the substrate.

Generally described, one or more embodiments are directed to semiconductor packages comprising a plurality of leads and methods of forming same. The plurality of leads include active leads that are electrically coupled to bond pads of a semiconductor die and thereby coupled to active components of the semiconductor die, and inactive leads that are not electrically coupled to bond pads of the semiconductor die. The active leads have surfaces that are exposed at a lower surface of the semiconductor package and forms lands, while the inactive leads are not exposed at the lower surface of the package.

Semiconductor packages with electromagnetic interference supported stacked die and a method of manufacture therefor is disclosed. The semiconductor packages may house a stack of dies in a system in a package (SiP) implementation, where one or more of the dies may be wire bonded to a semiconductor package substrate. The dies may be stacked in a partially overlapping, and staggered manner, such that portions of some dies may protrude out over an edge of a die that is below it. This dies stacking may define a cavity, and in some cases, wire bonds may be made to the protruding portions of the die. Underfill material may be provided in the cavity and cured to form an underfill support. Wire bonding of the bond pads overlying the cavity formed by the staggered stacking of the dies may be performed after the formation of the underfill support.

The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a substrate. The method also includes attaching an electronic component to the substrate. The method further includes attaching a fixing feature to an upper surface of the electronic component. In addition, the method includes forming a bonding wire connecting the substrate and the electronic component. The bonding wire is at least partially disposed on the fixing feature.

A semiconductor package includes a package substrate, a plurality of first semiconductor chips stacked on an upper surface of the package substrate in a stair-step configuration, the plurality of first semiconductor chips having an uppermost semiconductor chip at a first height from the upper surface of the package substrate, the uppermost semiconductor chip including a free end portion. Conductive wires respectively electrically connect chip pads of the first semiconductor chips to substrate pads of the package substrate. A plurality of first support structures each have a first end attached to the upper surface of the package substrate and an opposite second end attached to the free end portion of the uppermost semiconductor chip. The first support structures are inclined at an angle relative to the package substrate.