The method for fabricating a device includes the following successive steps: providing a first substrate made from silicon of (100), (110) or (111) orientation, from a material of III-IV type or from a material of II-VI type, provided with at least one salient metal pad, and providing a second substrate; fixing the first substrate with the second substrate, the at least one metal pad forming a blocking means preventing movement beyond a threshold position; and performing an anneal of the metal pad so as to melt the metal pad and eliminate the blocking means.

An integrated circuit package includes a first conductive element that is fabricated as part of the integrated circuit package and a micro-wire having a first end coupled to the first conductive element. The micro-wire has been fabricated ex-situ and is of a metal having a diameter of 10 microns or less.

A semiconductor device includes a shielding wire formed across a semiconductor die and an auxiliary wire supporting the shielding wire, thereby reducing the size of a package while shielding the electromagnetic interference generated from the semiconductor die. In one embodiment, the semiconductor device includes a substrate having at least one circuit device mounted thereon, a semiconductor die spaced apart from the circuit device and mounted on the substrate, a shielding wire spaced apart from the semiconductor die and formed across the semiconductor die, and an auxiliary wire supporting the shielding wire under the shielding wire and formed to be perpendicular to the shielding wire. In another embodiment, a bump structure is used to support the shielding wire. In a further embodiment, an auxiliary wire includes a bump structure portion and wire portion and both the bump structure portion and the wire portion are used to support the shielding wire.

A method for manufacturing a semiconductor device includes: a first bonding process including bonding, at a first bonding point, a tip of a wire held by a capillary; a first lifting process including moving the capillary upward; a first reverse process including moving the capillary in a direction that includes a component in a first direction that is from a second bonding point toward the first bonding point; a second lifting process including moving the capillary upward; a second reverse process including moving the capillary in the first direction; a third lifting process including moving the capillary upward; a forward process including moving the capillary toward the second bonding point; and a second bonding process including bonding the wire at the second bonding point. A movement distance of the capillary in the first lifting process is not less than a movement distance of the capillary in the second lifting process.

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

A method for processing an ultra-high density interconnect wire under light source guidance, comprising preparing a photo-thermal response conductive paste, and putting it into an air pressure injector; driving the air pressure injector; the air pressure injector extrudes the photo-thermal response conductive paste, so that the photo-thermal response conductive paste is connected with the first chip to form an interconnection wire; stopping extruding the photo-thermal response conductive paste, and driving the air pressure injector to pull off the interconnection wire; a linear light source emits light and irradiates on the interconnection wire to bend to an upper side of a second chip bonding pad; an extrusion mechanism presses a free end of the interconnection wire on the second chip bonding pad; the first chip and the second chip are subjected to glue dripping encapsulation.

A semiconductor package includes a first lead with first and second ends extending in the same direction as one another. At least one second lead has first and second ends and is partially surrounded by the first lead. A die pad is provided and a die is connected to the die pad. Wires electrically connect the die to the first lead and the at least one second lead. An insulating layer extends over the leads, the die pad, and the die such that the first end of the at least one second lead is exposed from the semiconductor package and the second end of the first lead is encapsulated entirely within the insulating layer.

In one example embodiment, a PCBA, an optoelectronic module, an electrical coupling, and/or a high speed interconnect may include a first contact pad, a second contact pad adjacent to and spaced apart from the first contact pad, a first wire coupled to the first contact pad via a first ball bump, and a second wire coupled to the second contact pad via a double ball bump.

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.