In an aspect, a system and method for assembling a semiconductor device on a receiving surface of a destination substrate is disclosed. In another aspect, a system and method for assembling a semiconductor device on a destination substrate with topographic features is disclosed. In another aspect, a gravity-assisted separation system and method for printing semiconductor device is disclosed. In another aspect, various features of a transfer device for printing semiconductor devices are disclosed.

Electronic devices are manufactured using a collective (wafer-scale) fabrication process. Electronic chips are mounted onto one face of a collective substrate wafer. A collective flexible sheet made of a heat-conductive material comprising a layer containing pyrolytic graphite is fixed to extend over a collective region extending over the electronic chips and over the collective substrate wafer between the electronic chips. The collective flexible sheet is then compressed. A dicing operation is then carried out in order to obtain electronic devices each including an electronic chip, a portion of the collective plate and a portion of the collective flexible sheet.

Semiconductor packages may include a molded interposer and semiconductor dice mounted on the molded interposer. The molded interposer may include two redistribution layer structures on opposite sides of a molding compound. Electrically conductive vias may connect the RDL structures through the molding compound, and passive devices may be embedded in the molding compound and electrically connected to one of the RDL structures. Each of the semiconductor dice may be electrically connected to, and have a footprint covering, a corresponding one of the passive devices to form a face-to-face connection between each of the semiconductor dice and the corresponding one of the passive devices.

Semiconductor packages may include a molded interposer and semiconductor dice mounted on the molded interposer. The molded interposer may include two redistribution layer structures on opposite sides of a molding compound. Electrically conductive vias may connect the RDL structures through the molding compound, and passive devices may be embedded in the molding compound and electrically connected to one of the RDL structures. Each of the semiconductor dice may be electrically connected to, and have a footprint covering, a corresponding one of the passive devices to form a face-to-face connection between each of the semiconductor dice and the corresponding one of the passive devices.

A package structure and a method for manufacturing the same are provided. The package structure includes an electronic device, a heat spreader, an intermediate layer and an encapsulant. The electronic device includes a plurality of electrical contacts. The intermediate layer is interposed between the electronic device and the heat spreader. The intermediate layer includes a sintered material. The encapsulant encapsulates the electronic device. A surface of the encapsulant is substantially coplanar with a plurality of surfaces of the electrical contacts.

A package structure and a method for manufacturing the same are provided. The package structure includes an electronic device, a heat spreader, an intermediate layer and an encapsulant. The electronic device includes a plurality of electrical contacts. The intermediate layer is interposed between the electronic device and the heat spreader. The intermediate layer includes a sintered material. The encapsulant encapsulates the electronic device. A surface of the encapsulant is substantially coplanar with a plurality of surfaces of the electrical contacts.

A manufacturing method of a mounting structure includes: a step of preparing a mounting member including a first circuit member and a plurality of second circuit members placed on the first circuit member; a disposing step of disposing a thermosetting sheet and a thermoplastic sheet on the mounting member, with the thermosetting sheet interposed between the thermoplastic sheet and the first circuit member; a first sealing step of pressing a stack of the thermosetting sheet and the thermoplastic sheet against the first circuit member, and heating the stack, to seal the second circuit members and to cure the thermosetting sheet into a cured layer; and a removal step of removing the thermoplastic sheet from the cured layer. At least one of the second circuit members is a hollow member having a space from the first circuit member, and in the first sealing step, the second circuit members are sealed so as to maintain the space.

A manufacturing method of a mounting structure includes: a step of preparing a mounting member including a first circuit member and a plurality of second circuit members placed on the first circuit member; a disposing step of disposing a thermosetting sheet and a thermoplastic sheet on the mounting member, with the thermosetting sheet interposed between the thermoplastic sheet and the first circuit member; a first sealing step of pressing a stack of the thermosetting sheet and the thermoplastic sheet against the first circuit member, and heating the stack, to seal the second circuit members and to cure the thermosetting sheet into a cured layer; and a removal step of removing the thermoplastic sheet from the cured layer. At least one of the second circuit members is a hollow member having a space from the first circuit member, and in the first sealing step, the second circuit members are sealed so as to maintain the space.

A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate. First and second encapsulants are deposited over the first semiconductor die and substrate. A first build-up interconnect structure is formed over the substrate after depositing the second encapsulant. The top package is disposed over the bottom package. The bottom package has a second semiconductor die and modular interconnect units disposed around the second semiconductor die. A second build-up interconnect structure is formed over the second semiconductor die and modular interconnect unit. The modular interconnect units include a plurality of conductive vias and a plurality of contact pads electrically connected to the conductive vias. The I/O pattern of the build-up interconnect structure on the top semiconductor package is designed to coincide with the I/O pattern of the modular interconnect units.

A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate. First and second encapsulants are deposited over the first semiconductor die and substrate. A first build-up interconnect structure is formed over the substrate after depositing the second encapsulant. The top package is disposed over the bottom package. The bottom package has a second semiconductor die and modular interconnect units disposed around the second semiconductor die. A second build-up interconnect structure is formed over the second semiconductor die and modular interconnect unit. The modular interconnect units include a plurality of conductive vias and a plurality of contact pads electrically connected to the conductive vias. The I/O pattern of the build-up interconnect structure on the top semiconductor package is designed to coincide with the I/O pattern of the modular interconnect units.