A die and a substrate are provided. The die comprises at least one integrated circuit chip, and the substrate comprises first and second subsets of conductive pillars extending at least partially therethrough. Each of the first subset of conductive pillars comprises a protrusion bump pad protruding from a surface of the substrate, and the second subset of conductive pillars each partially form a trace recessed within the surface of the substrate. The die is coupled to the substrate via a plurality of conductive bumps each extending between one of the protrusion bump pads and the die.

An anisotropic conductive film composition, an anisotropic conductive film prepared using the same, and a connection structure using the same, the anisotropic conductive film including a binder resin; a curable alicyclic epoxy compound; a curable oxetane compound; a quaternary ammonium catalyst; and conductive particles, wherein the anisotropic conductive film has a heat quantity variation rate of about 15% or less, as measured by differential scanning calorimetry (DSC) and calculated by Equation 1:
Heat quantity variation rate (%)=[(H.sub.0H.sub.1)/H.sub.0]100Equation 1 wherein H.sub.0 is a DSC heat quantity of the anisotropic conductive film, as measured at 25 C. and a time point of 0 hr, and H.sub.1 is a DSC heat quantity of the anisotropic conductive film, as measured after being left at 40 C. for 24 hours.

A die and a substrate are provided. The die comprises at least one integrated circuit chip, and the substrate comprises first and second subsets of conductive pillars extending at least partially therethrough. Each of the first subset of conductive pillars comprises a protrusion bump pad protruding from a surface of the substrate, and the second subset of conductive pillars each partially form a trace recessed within the surface of the substrate. The die is coupled to the substrate via a plurality of conductive bumps each extending between one of the protrusion bump pads and the die.

Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

A bonding method including the steps of: providing a first substrate comprising a first face comprising a first dielectric material and first metal pads, providing a second substrate comprising a first face comprising a second dielectric material, second metal pads, and a metal portion, placing the first face of the first substrate (100) in contact with the first face of the second substrate, so that, in a first zone the first metal pads are disposed facing the second metal pads and, in a second zone, the first metal pads are disposed facing the second dielectric material and the metal portion is disposed facing the first dielectric material, and performing a heat treatment.

An example device in accordance with an aspect of the present disclosure includes a first layer and a second layer to be bonded to the first layer. The first and second layers are materials that generate gas byproducts when bonded, and the first and/or second layers is/are compatible with photonic device operation based on a separation distance. At least one bonding interface layer is to establish the separation distance for photonic device operation, and is to prevent gas trapping and to facilitate bonding between the first layer and the second layer.

Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.

According to one embodiment, a semiconductor device includes a first substrate, a second substrate joined to the first substrate. A first region of the semiconductor device that includes a peripheral circuit is between the first substrate and the second substrate. A second region that includes a memory cell array is between the first region and the second substrate. A layer that is embedded in the second substrate has a Young's modulus that is higher than that of silicon and/or an internal stress that is higher than that of silicon oxide.