Patent classifications
H01L2924/07001
GALVANIC CORROSION PROTECTION FOR SEMICONDUCTOR PACKAGES
Techniques of protecting cored or coreless semiconductor packages having materials formed from dissimilar metals from galvanic corrosion are described. An exemplary semiconductor package comprises one or more build-up layers; first and second semiconductor components (e.g., die, EMIB, etc.) on or embedded in the one or more build-up layers. The first semiconductor component may be electrically coupled to the second semiconductor component via a contact pad and an interconnect structure that are formed in the one or more build-up layers. The contact pad can comprise a contact region, a non-contact region, and a gap region that separates the contact region from the non-contact region. Coupling of the contact pad and an interconnect structure is performed by coupling only the contact region with the interconnect structure. Also, a surface area of the contact region can be designed to substantially equal to a surface area of the interconnect structure.
GALVANIC CORROSION PROTECTION FOR SEMICONDUCTOR PACKAGES
Techniques of protecting cored or coreless semiconductor packages having materials formed from dissimilar metals from galvanic corrosion are described. An exemplary semiconductor package comprises one or more build-up layers; first and second semiconductor components (e.g., die, EMIB, etc.) on or embedded in the one or more build-up layers. The first semiconductor component may be electrically coupled to the second semiconductor component via a contact pad and an interconnect structure that are formed in the one or more build-up layers. The contact pad can comprise a contact region, a non-contact region, and a gap region that separates the contact region from the non-contact region. Coupling of the contact pad and an interconnect structure is performed by coupling only the contact region with the interconnect structure. Also, a surface area of the contact region can be designed to substantially equal to a surface area of the interconnect structure.
Method for manufacturing semiconductor device
There is disclosed a method for manufacturing a semiconductor device comprising a semiconductor chip having a connection portion and a wiring circuit board having a connection portion, the respective connection portions being electrically connected to each other, or a semiconductor device comprising a plurality of semiconductor chips having connection portions, the respective connection portions being electrically connected to each other. The connection portions consist of metal. The above described method comprises: (a) a first step of press-bonding the semiconductor chip and the wiring circuit board or the semiconductor chips to each other so that the respective connection portions are in contact with each other with a semiconductor adhesive interposed therebetween, at a temperature lower than a melting point of the metal of the connection portion, to obtain a temporarily connected body; (b) a second step of sealing at least a part of the temporarily connected body with a sealing resin to obtain a sealed temporarily connected body; and (c) a third step of heating the sealed temporarily connected body at a temperature equal to or higher than the melting point of the metal of the connection portion, to obtain a sealed connected body.
Method for manufacturing semiconductor device
There is disclosed a method for manufacturing a semiconductor device comprising a semiconductor chip having a connection portion and a wiring circuit board having a connection portion, the respective connection portions being electrically connected to each other, or a semiconductor device comprising a plurality of semiconductor chips having connection portions, the respective connection portions being electrically connected to each other. The connection portions consist of metal. The above described method comprises: (a) a first step of press-bonding the semiconductor chip and the wiring circuit board or the semiconductor chips to each other so that the respective connection portions are in contact with each other with a semiconductor adhesive interposed therebetween, at a temperature lower than a melting point of the metal of the connection portion, to obtain a temporarily connected body; (b) a second step of sealing at least a part of the temporarily connected body with a sealing resin to obtain a sealed temporarily connected body; and (c) a third step of heating the sealed temporarily connected body at a temperature equal to or higher than the melting point of the metal of the connection portion, to obtain a sealed connected body.
SEMICONDUCTOR DEVICE
An object of the present invention is to provide a semiconductor device in which peeling between a mold resin and a substrate is suppressed. A semiconductor device 1 includes a semiconductor chip 20 and a substrate 10 that are molded with a mold resin layer 40. The semiconductor device 1 includes a resin layer 50 having a thickness of 200 nm or less different from the mold resin layer 40 between the cured mold resin layer 40 and the substrate 10. The resin layer 50 present between the mold resin layer 40 and the substrate 10 is preferably present on a periphery of 30% or more of the chip when an entire peripheral length of the chip is 100%.
SEMICONDUCTOR DEVICE
An object of the present invention is to provide a semiconductor device in which peeling between a mold resin and a substrate is suppressed. A semiconductor device 1 includes a semiconductor chip 20 and a substrate 10 that are molded with a mold resin layer 40. The semiconductor device 1 includes a resin layer 50 having a thickness of 200 nm or less different from the mold resin layer 40 between the cured mold resin layer 40 and the substrate 10. The resin layer 50 present between the mold resin layer 40 and the substrate 10 is preferably present on a periphery of 30% or more of the chip when an entire peripheral length of the chip is 100%.
CONNECTION STRUCTURE
A method for manufacturing connection structure, the method includes arranging a first composite on a first surface of a first member where a first electrode is located and arranging conductive particles on the first electrode, arranging a second composite on a region other than the first electrode of the first surface, arranging the first surface and a second surface of a second member where a second electrode is located, so that the first electrode and the second electrode are opposed to each other, pressing the first member and the second member, and curing the first composite and the second composite.
CONNECTION STRUCTURE
A method for manufacturing connection structure, the method includes arranging a first composite on a first surface of a first member where a first electrode is located and arranging conductive particles on the first electrode, arranging a second composite on a region other than the first electrode of the first surface, arranging the first surface and a second surface of a second member where a second electrode is located, so that the first electrode and the second electrode are opposed to each other, pressing the first member and the second member, and curing the first composite and the second composite.
Engineered polymer-based electronic materials
A composition for use in an electronic assembly process, the composition comprising a filler dispersed in an organic medium, wherein: the organic medium comprises a polymer; the filler comprises one or more of graphene, functionalized graphene, graphene oxide, a polyhedral oligomeric silsesquioxane, graphite, a 2D material, aluminum oxide, zinc oxide, aluminum nitride, boron nitride, silver, nano fibers, carbon fibers, diamond, carbon nanotubes, silicon dioxide and metal-coated particles, and the composition comprises from 0.001 to 40 wt. % of the filler based on the total weight of the composition.
Engineered polymer-based electronic materials
A composition for use in an electronic assembly process, the composition comprising a filler dispersed in an organic medium, wherein: the organic medium comprises a polymer; the filler comprises one or more of graphene, functionalized graphene, graphene oxide, a polyhedral oligomeric silsesquioxane, graphite, a 2D material, aluminum oxide, zinc oxide, aluminum nitride, boron nitride, silver, nano fibers, carbon fibers, diamond, carbon nanotubes, silicon dioxide and metal-coated particles, and the composition comprises from 0.001 to 40 wt. % of the filler based on the total weight of the composition.