An integrated circuit (IC) packaging arrangement for surface mounting of the IC includes a package body that encapsulates one or more IC dies. The package body according to some embodiments has rectangular aspect ratio with a length dimension and a width dimension of different size. The IC packaging according to some embodiments includes leadless surface-mount electrical contacts. According to some embodiments, the leadless surface-mount contacts are situated in clusters at opposite ends of the length dimension of the IC body.

Described herein are semiconductor devices and structures with improved power handling and heat dissipation. Embodiments are suitable for implementation in gallium nitride. Devices may be provided as individual square or diamond-shaped dies having electrode terminals at the die corners, tapered electrode bases, and interdigitated electrode fingers. Device matrix structures include a plurality of device dies arranged on a substrate in a matrix configuration with interdigitated conductors. Device lattice structures are based on a unit cell comprising a plurality of individual devices, the unit cells disposed on a chip with geometric periodicity. Also described herein are methods for implementing the semiconductor devices and structures.

Described herein are semiconductor devices and structures with improved power handling and heat dissipation. Embodiments are suitable for implementation in gallium nitride. Devices may be provided as individual square or diamond-shaped dies having electrode terminals at the die corners, tapered electrode bases, and interdigitated electrode fingers. Device matrix structures include a plurality of device dies arranged on a substrate in a matrix configuration with interdigitated conductors. Device lattice structures are based on a unit cell comprising a plurality of individual devices, the unit cells disposed on a chip with geometric periodicity. Also described herein are methods for implementing the semiconductor devices and structures.

An integrated circuit (IC) packaging arrangement for surface mounting of the IC includes a package body that encapsulates one or more IC dies. The package body according to some embodiments has rectangular aspect ratio with a length dimension and a width dimension of different size. The IC packaging according to some embodiments includes leadless surface-mount electrical contacts. According to some embodiments, the leadless surface-mount contacts are situated in clusters at opposite ends of the length dimension of the IC body.

Provided is a semiconductor device which can be prevented from increasing in size. The semiconductor device includes a semiconductor chip having a first main surface and a second main surface opposite to the first main surface and a wiring substrate over which the semiconductor chip is mounted such that the second main surface of the semiconductor chip faces a first main surface of the wiring substrate. Over the second main surface of the semiconductor chip, a plurality of first terminals connected with a first circuit and a plurality of second terminals connected with a second circuit are arranged. An arrangement pattern of the plurality of first terminals and an arrangement pattern of the plurality of second terminals include the same arrangement pattern. In a region of the wiring substrate where the first circuit is close to the second circuit when viewed from the first main surface of the semiconductor chip, a voltage line which supplies a power supply voltage to the first circuit is formed. In a region of the wiring substrate where the second circuit is close to the first circuit, a voltage line which supplies the power supply voltage to the second circuit is formed.

An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a conductive layer underlying the sintered metallic layer, and a conductive substrate underlying the conductive layer.

Provided is a semiconductor device which can be prevented from increasing in size. The semiconductor device includes a semiconductor chip having a first main surface and a second main surface opposite to the first main surface and a wiring substrate over which the semiconductor chip is mounted such that the second main surface of the semiconductor chip faces a first main surface of the wiring substrate. Over the second main surface of the semiconductor chip, a plurality of first terminals connected with a first circuit and a plurality of second terminals connected with a second circuit are arranged. An arrangement pattern of the plurality of first terminals and an arrangement pattern of the plurality of second terminals include the same arrangement pattern. In a region of the wiring substrate where the first circuit is close to the second circuit when viewed from the first main surface of the semiconductor chip, a voltage line which supplies a power supply voltage to the first circuit is formed. In a region of the wiring substrate where the second circuit is close to the first circuit, a voltage line which supplies the power supply voltage to the second circuit is formed.

Embodiments of the present disclosure are directed toward integrated circuit (IC) packaging techniques and configurations for small form-factor or wearable devices. In one embodiment, an apparatus may include a substrate having a first side and a second side disposed opposite to the first side and a sidewall disposed between the first side and the second side, the sidewall defining a perimeter of the substrate, and a plurality of through-substrate vias (TSVs) disposed between the first side and the second side of the substrate, and a first dielectric layer disposed on the first side and including electrical routing features to route electrical signals of one or more dies in a plane of the first dielectric layer. Other embodiments may be described and/or claimed.

An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a thermally conductive flow layer underlying the sintered metallic layer, and a thermally conductive substrate underlying the thermally conductive flow layer.

Provided is a semiconductor device which can be prevented from increasing in size. The semiconductor device includes a semiconductor chip having a first main surface and a second main surface opposite to the first main surface and a wiring substrate over which the semiconductor chip is mounted such that the second main surface of the semiconductor chip faces a first main surface of the wiring substrate. Over the second main surface of the semiconductor chip, a plurality of first terminals connected with a first circuit and a plurality of second terminals connected with a second circuit are arranged. An arrangement pattern of the plurality of first terminals and an arrangement pattern of the plurality of second terminals include the same arrangement pattern. In a region of the wiring substrate where the first circuit is close to the second circuit when viewed from the first main surface of the semiconductor chip, a voltage line which supplies a power supply voltage to the first circuit is formed. In a region of the wiring substrate where the second circuit is close to the first circuit, a voltage line which supplies the power supply voltage to the second circuit is formed.