Systems and methods for applying solder to a pin. The methods comprising: disposing a given amount of solder on a non-wetable surface of a planar substrate; aligning the pin with the solder disposed on the non-wetable surface of the planar substrate; inserting the pin in the solder; and/or performing a reflow process to cause the solder to transfer from the planar substrate to the pin.

An apparatus including a carrier mount having a staircase of steps in an opening in the carrier mount and a plurality of dies, each one of the dies having at least a portion of an edge of a major surface thereof located on one of the steps corresponding to the one of the dies such that the dies form a stack, major surfaces of the dies being substantially parallel in the stack, each of the dies having one or more electro-optical devices thereon.

A semiconductor package includes a redistribution substrate having a first surface and a second surface which are opposite to each other, a semiconductor chip mounted on the first surface of the redistribution substrate, an under bump interconnection layer on the second surface of the redistribution substrate, an electronic device mounted on the under bump interconnection layer, and a solder bump disposed on the under bump interconnection layer and horizontally spaced apart from the electronic device. The under bump interconnection layer includes conductive patterns respectively connected to the electronic device and the solder bump, and a passivation layer covering the conductive patterns. The passivation layer includes a plurality of trenches disposed between the electronic device and the solder bump.

Systems and methods for applying solder to a pin. The methods comprising: disposing a given amount of solder on a non-wetable surface of a planar substrate; aligning the pin with the solder disposed on the non-wetable surface of the planar substrate; inserting the pin in the solder; and performing a reflow process to cause the solder to transfer from the planar substrate to the pin.

An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.

An apparatus is provided which comprises: one or more first conductive contacts on a first substrate surface, one or more second conductive contacts on a second substrate surface opposite the first substrate surface, a core layer comprising glass between the first and the second substrate surfaces, and one or more thin film capacitors on the glass core conductively coupled with one of the first conductive contacts and one of the second conductive contacts, wherein the thin film capacitor comprises a first metal layer on a surface of the glass core, a thin film dielectric material on a surface of the first metal layer, and a second metal layer on a surface of the thin film dielectric material. Other embodiments are also disclosed and claimed.

Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure incudes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.

A display device includes a display panel having a display area comprising pixels and a non-display area surrounding the display area, an encapsulation substrate which faces the display panel and is disposed on a surface of the display panel, and a sealing member disposed in the non-display area and interposed between the display panel and the encapsulation substrate for bonding. The display panel comprises a base substrate and a first conductive layer disposed on a first surface of the base substrate, the base substrate provides a through hole defined in a part of the non-display area to penetrate the base substrate in a thickness direction, the first conductive layer comprises a signal line disposed in a part of the non-display area and filling the through hole, and the sealing member does not overlap the first conductive layer and the through hole in the thickness direction.

A package structure includes: a first dielectric layer having a first surface and a second surface opposing the first surface; a semiconductor chip embedded in the first dielectric layer in a manner that the semiconductor chip protrudes from the second surface, and having an active surface and an inactive surface opposing the active surface, electrode pads being disposed on the active surface and in the first dielectric layer, the inactive surface and a part of a side surface adjacent the inactive surface protruding from the second surface; a first circuit layer disposed on the first surface; a built-up structure disposed on the first surface and the first circuit layer; and an insulating protective layer disposed on the built-up structure, a plurality of cavities being formed in the insulating protective layer for exposing a part of a surface of the built-up structure. The package structure includes only one built-up structure.

A package structure includes: a first dielectric layer having a first surface and a second surface opposing the first surface; a semiconductor chip embedded in the first dielectric layer in a manner that the semiconductor chip protrudes from the second surface, and having an active surface and an inactive surface opposing the active surface, electrode pads being disposed on the active surface and in the first dielectric layer, the inactive surface and a part of a side surface adjacent the inactive surface protruding from the second surface; a first circuit layer disposed on the first surface; a built-up structure disposed on the first surface and the first circuit layer; and an insulating protective layer disposed on the built-up structure, a plurality of cavities being formed in the insulating protective layer for exposing a part of a surface of the built-up structure. The package structure includes only one built-up structure.