Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate with a cavity, where the first substrate comprises glass. In an embodiment, a second substrate is in the cavity. In an embodiment, a bond film covers a bottom of the second substrate and extends up sidewalls of the second substrate.

A semiconductor device including a plurality of solder balls on a surface the semiconductor device, and a retaining body associated with a first solder ball of the plurality of solder balls, separating the first solder ball from at least a second solder ball of the plurality of solder balls. The retaining body includes a conductive portion and an insulating portion configured to cover the conductive portion. Also, a method of manufacturing a semiconductor device, including acts of forming a plurality of retaining bodies on a surface of a wiring substrate, each retaining body comprising a conductive portion and an insulating portion covering the conductive portion, each retaining body forming an opening section, and forming a solder ball in the opening section formed by each of the retaining bodies.

A semiconductor pressure sensor of the invention, includes: a base body (1) including: a lead frame (4) having a first surface and a second surface; and a support (5) that supports the lead frame (4) and is made of a resin; a pressure sensor chip (2) provided on the first surface of the lead frame (4); and a controller (3) that is provided on the second surface of the lead frame (4), is implanted in the support (5), is formed in the shape having a plurality of surfaces, includes a stress relief layer (32, 33, 34, 35, 36) that is formed on at least one of the plurality of surfaces and has a Young's modulus lower than that of the support (5), and receives a sensor signal output from the pressure sensor chip (2) aid thereby outputs a pressure detection, the pressure sensor chip (2) at least partially overlapping the controller (3) in plan view.

Integrated circuit (IC) packages employing a re-distribution layer (RDL) substrate(s) with photosensitive non-polymer dielectric material layers for increased package rigidity, and related fabrication methods. To reduce or minimize warpage of an IC package employing a RDL substrate, the RDLs of the RDL substrate are photosensitive non-polymer dielectric material layers. The photosensitive non-polymer dielectric material layers can exhibit increased rigidity as a result of being hardened when exposed to light and cured during fabrication of the RDL substrate. The photosensitive non-polymer dielectric material layers can also exhibit increased rigidity as a result of being an inorganic polymer (e.g., SiOx, SiN material) that has a higher material modulus for increased stiffness and/or a lower coefficient of thermal expansion (CTE) for reduced thermal contraction and expansion, as opposed to for example, an organic polymer material (e.g., Polyimide) which has less stiffness and a higher CTE.

In a capacitor, a width in a length direction of a first portion of a third outer electrode, which is a portion located on a first side surface, is greater than a width in a length direction of a second portion of the third outer electrode, which is a portion located on a first main surface. The first portion of the third outer electrode does not extend to first and second end surfaces.

The present technology relates to a semiconductor device, a manufacturing method for the same, and an electronic apparatus, in which a chip size package can be more easily achieved by using flexible printed circuits. Provided is a semiconductor device including: a solid-state image sensor having a pixel array unit in which a plurality of pixels each having a photoelectric conversion element is two-dimensionally arranged in a matrix; and a flexible printed circuit having wiring adapted to connect a pad portion provided on an upper surface side to be located on a light receiving surface side of the solid-state image sensor to an external terminal provided on a lower surface side opposite to the upper surface side, in which the flexible printed circuit is arranged along respective surfaces of the solid-state image sensor such that a position of an end portion located on the upper surface side becomes a position different from a position in a space above the light receiving surface. The present technology can be applied at the time of packaging a CMOS image sensor, for example.

A method of fabricating a package includes providing a mold substrate supporting dies in cavities of a fan-out substrate, detecting positions of the dies with respect to the fan-out substrate, and forming interconnection lines. At least one of the interconnection lines includes a first portion extending from the fan-out substrate to a target position on the cavity disposed between the fan-out substrate and one of the dies the one of the dies disposed at a detected position different from the target position, and a second portion extending from the one die to the fan-out substrate.

A method of fabricating a package includes providing a mold substrate supporting dies in cavities of a fan-out substrate, detecting positions of the dies with respect to the fan-out substrate, and forming interconnection lines. At least one of the interconnection lines includes a first portion extending from the fan-out substrate to a target position on the cavity disposed between the fan-out substrate and one of the dies the one of the dies disposed at a detected position different from the target position, and a second portion extending from the one die to the fan-out substrate.

Provided is a semiconductor package including a package substrate, a connection substrate mounted on the package substrate, and including a first conductive connection structure, a first integrated circuit device mounted on the package substrate, and a second integrated circuit device disposed on the connection substrate and the first integrated circuit device, and including a first portion overlapping the first integrated circuit device and a second portion overlapping the connection substrate, wherein one of the first integrated circuit device and the second integrated circuit device includes a photonic integrated circuit device to which an optical fiber is attached, and the other of the first integrated circuit device and the second integrated circuit device includes an electronic integrated circuit device, and wherein the second integrated circuit device is electrically connected to the package substrate via the first conductive connection structure of the connection substrate.

A glass core substrate includes a first glass layer; a second glass layer disposed on the first glass layer; a third glass layer disposed on the second glass layer; a first bonding layer disposed between the first glass layer and the second glass layer; a second bonding layer disposed between the second glass layer and the third glass layer; and a conductive connector, passing through the first glass layer, the first bonding layer, the second glass layer, the second bonding layer, and the third glass layer, wherein the conductive connector is configured to provide a vertical conductive path penetrating through the first glass layer, the first bonding layer, the second glass layer, the second bonding layer, and the third glass layer. A manufacturing method of a glass core substrate is also provided.