Patent classifications
H01L2924/1615
Packaging structures with improved adhesion and strength
According to various aspects and embodiments, a support structure for packaging an electronic device is provided. In one example, a packaged electronic device includes a substrate, at least one electronic device disposed on the substrate, an encapsulation structure disposed on the substrate and having a wall that forms a perimeter around the at least one electronic device, and at least one support structure formed from a photosensitive polymer and disposed adjacent the wall of the encapsulation structure. The at least one support structure has a configuration that provides at least one of increased adhesion and mechanical strength to the encapsulation structure.
HEAT SPREADING PLATE
A heat spreading plate is suitable to be a top cover of a chip package structure. The heat spreading plate includes a main body and an isolating frame. The main body includes a plurality of metal sheets which are arranged spaced apart from one another totally and capable of thermally connecting different working chips mounted within the chip package structure, respectively. A gap is formed between any two neighboring ones of the metal sheets to completely separate them. The isolating frame surrounds the outer edges of the metal sheets and fills into the gaps for fixedly holding the metal sheets together. One surface of the isolating frame is formed with a plurality of hollow recesses, and each of the metal sheets is exposed outwards from one of the hollow recesses.
INTEGRATED HEAT SPREADER (IHS) WITH SOLDER THERMAL INTERFACE MATERIAL (STIM) BLEED-OUT RESTRICTING FEATURE
Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A solder thermal interface material (STIM) may be coupled with the die such that the die is between the STIM and the package substrate. An integrated heat spreader (IHS) may be coupled with the STIM such that the STIM is between the IHS and the die, and the IHS may include a feature that is to control bleed-out of the STIM during STIM reflow based on surface tension of the STIM. Other embodiments may be described or claimed.
System and method for bonding package lid
Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side of a substrate, a seal ring disposed in the at least one dielectric layer, and at least one groove in the seal ring. A lid is disposed over the workpiece, the workpiece extending into a recess in the lid and a first thermal interface material (TIM) contacts the seal ring and the lid, with the first TIM extending into the at least one groove. The workpiece is mounted to the package carrier. A die is mounted over a first side of workpiece and disposed in the recess. A first underfill a disposed under the die and a second underfill is disposed between the workpiece and the package carrier. The first TIM is disposed between the first underfill and the second underfill.
MULTI-CHIP PACKAGE WITH OFFSET 3D STRUCTURE
Various semiconductor chip devices and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that has a reconstituted semiconductor chip package that includes an interposer that has a first side and a second and opposite side and a metallization stack on the first side, a first semiconductor chip on the metallization stack and at least partially encased by a dielectric layer on the metallization stack, and plural semiconductor chips positioned over and at least partially laterally overlapping the first semiconductor chip.
ELECTRONIC DEVICE AND CORRESPONDING MANUFACTURING METHOD
An electronic integrated circuit (IC) component is mounted to a substrate. A cap member is applied onto the substrate and covers the electronic IC component. The cap member includes an outer wall defining an opening and an inner wall surrounding the electronic IC component. The inner wall extends from a proximal end at the substrate towards a distal end facing the opening in the outer wall to provide a reception chamber for the electronic IC component and a peripheral chamber between the inner wall and the outer wall of the cap member. An encapsulant material is provided in the reception chamber to seal the electronic IC component without being present in the peripheral chamber.
Multi-chip package with offset 3D structure
Various semiconductor chip devices and methods of manufacturing the same are disclosed. In one aspect, a semiconductor chip device is provided that has a reconstituted semiconductor chip package that includes an interposer that has a first side and a second and opposite side and a metallization stack on the first side, a first semiconductor chip on the metallization stack and at least partially encased by a dielectric layer on the metallization stack, and plural semiconductor chips positioned over and at least partially laterally overlapping the first semiconductor chip.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
A method for forming a packaged electronic device includes providing a substrate having a first major surface and an opposing second major surface. The method includes attaching an electronic device to the first major surface of the substrate and providing a first conductive structure coupled to at least a first portion of the substrate. The method includes forming a dielectric layer overlying at least part of the first conductive structure. The method includes forming a conductive layer overlying the dielectric layer and connected to a second portion of the substrate. The first conductive structure, the dielectric layer, and conductive layer are configured as a capacitor structure and further configured as one or more of an enclosure structure or a stiffener structure for the packaged electronic device.
Multiple-chip package with multiple thermal interface materials
A multiple chip package is described with multiple thermal interface materials. In one example, a package has a substrate, a first semiconductor die coupled to the substrate, a second semiconductor die coupled to the substrate, a heat spreader coupled to the die, wherein the first die has a first distance to the heat spreader and the second die has a second distance to the heat spreader, a first filled thermal interface material (TIM) between the first die and the heat spreader to mechanically and thermally couple the heat spreader to the die, and a second filled TIM between the second die and the heat spreader to mechanically and thermally couple the heat spreader to the second die.
PACKAGING STRUCTURES WITH IMPROVED ADHESION AND STRENGTH
According to various aspects and embodiments, a support structure for packaging an electronic device is provided. In one example, a packaged electronic device includes a substrate, at least one electronic device disposed on the substrate, an encapsulation structure disposed on the substrate and having a wall that forms a perimeter around the at least one electronic device, and at least one support structure formed from a photosensitive polymer and disposed adjacent the wall of the encapsulation structure. The at least one support structure has a configuration that provides at least one of increased adhesion and mechanical strength to the encapsulation structure.