H01L2924/1711

Semiconductor device and manufacturing method thereof

A semiconductor device includes a die pad, a semiconductor chip with a bonding pad being formed, a lead one end of which is located in the vicinity of the semiconductor chip, a coupling wire that connects an electrode and the lead, and a sealing body that seals the semiconductor chip, the coupling wire, a part of the lead, and a part of the die pad. A lower surface of the die pad is exposed from a lower surface of the sealing body, the die pad and the coupling wire are comprised of copper, and a thickness of the semiconductor chip is larger than the sum of a thickness of the die pad and a thickness from an upper surface of the semiconductor chip to an upper surface of the sealing body.

Integrated circuit device with plating on lead interconnection point and method of forming the device
10062639 · 2018-08-28 · ·

An integrated circuit (IC) device includes an IC die and a plurality of leads. Each lead includes an unplated proximal end including a first material, and an unplated distal end including the first material. A plated bond wire portion extends between the proximal and distal ends and includes the first material and a plating of a second material thereon. A plurality of bond wires extend between the IC die and the plated bond wire portions of the leads. An encapsulation material surrounds the IC die and bond wires so that the unplated proximal end and plated bond wire portion of each lead are covered by the encapsulation material.

Isolator with reduced susceptibility to parasitic coupling

A capacitive isolation system, capacitive isolator, and method of operating the same are disclosed. The capacitive isolation system is described to include a first semiconductor die and a second semiconductor die each having capacitive elements established thereon and positioned in a face-to-face configuration. An isolation layer is provided between the first and second semiconductor die so as to establish an isolation boundary therebetween. Capacitive coupling is used to carry information across the isolation boundary.

Strip-shaped substrate for producing chip carriers, electronic module with a chip carrier of this type, electronic device with a module of this type, and method for producing a substrate

A strip-shaped substrate made from a film includes a plurality of units for producing chip carriers. Each unit has a chip island for fixing a semiconductor chip, electrodes for electrical connection of the semiconductor chip, and through-openings for structuring the unit. At least one through-opening forms an anchoring edge for a casting compound for encapsulating the semiconductor chip. A surface section of the film abutting the through-opening is chamfered to form the anchoring edge. The anchoring edge protrudes past the side of the film on which the chip island is arranged.

SEMICONDUCTOR DEVICE AND MOUTING STRUCTURE OF SEMICONDUCTOR DEVICE
20180053891 · 2018-02-22 ·

The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor element, a plurality of terminals, and a sealing resin. The semiconductor element has a front surface and a back surface. The front surface and the back surface face in opposite directions to each other in a thickness direction of the semiconductor element. The plurality of terminals are disposed at a distance from the semiconductor element and are electrically connected to the front surface. The sealing resin has a first surface facing in a same direction as the direction in which the front surface faces. Each of the plurality of terminals has a main surface exposed from the first surface.

Molded leadframe substrate semiconductor package

A process for forming land grid array semiconductor packages includes a leadframe that is supported by a substrate comprising mold compound. In some embodiments, at least one die is electrically coupled to the leadframe by bondwires. The package comprises a second mold compound to act as an encapsulant. An apparatus for forming a land grid array semiconductor package includes means for molding a leadframe, assembling thereon at least one semiconductor device, applying a second mold, and singulating to form individual devices. A land grid array package comprises a leadframe, a substrate for supporting the leadframe, at least one semiconductor device and a mold compound.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
20180040552 · 2018-02-08 ·

A semiconductor device includes a die pad, a semiconductor chip with a bonding pad being formed, a lead one end of which is located in the vicinity of the semiconductor chip, a coupling wire that connects an electrode and the lead, and a sealing body that seals the semiconductor chip, the coupling wire, a part of the lead, and a part of the die pad. A lower surface of the die pad is exposed from a lower surface of the sealing body, the die pad and the coupling wire are comprised of copper, and a thickness of the semiconductor chip is larger than the sum of a thickness of the die pad and a thickness from an upper surface of the semiconductor chip to an upper surface of the sealing body.

ELECTRONIC COMPONENT WITH IMPROVED BOARD LEVEL RELIABILITY
20240404937 · 2024-12-05 ·

A device may include a circuit board with a top side and a bottom side, wherein the circuit board defines a horizontal xy-plane and a vertical z-direction which is perpendicular to the horizontal xy-plane. A device may include a die attached to the top side of the circuit board, a top package, wherein the top package is attached to the top side of the circuit board and surrounds the die. A device may include a bottom package, wherein the bottom package is attached to the bottom side of the circuit board and a bottom surface of the bottom package forms the bottom side of the electronic component, wherein the bottom package includes a side wall having an outside surface, and wherein the outside surface comprises a metallic surface.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a die pad, a semiconductor chip with a bonding pad being formed, a lead one end of which is located in the vicinity of the semiconductor chip, a coupling wire that connects an electrode and the lead, and a sealing body that seals the semiconductor chip, the coupling wire, a part of the lead, and a part of the die pad. A lower surface of the die pad is exposed from a lower surface of the sealing body, the die pad and the coupling wire are comprised of copper, and a thickness of the semiconductor chip is larger than the sum of a thickness of the die pad and a thickness from an upper surface of the semiconductor chip to an upper surface of the sealing body.

Packaged device with additive substrate surface modification

A method of lead frame surface modification includes providing at least one pre-fabricated metal lead frame or package substrate (substrate) unit including a base metal having a die pad and a plurality of contact regions surrounding the die pad. An ink including a material that is a solid or a precursor for a solid that forms a solid upon a curing step or a sintering step that removes a liquid carrier is additively deposited including onto at least one of (i) a region of the die pad and (ii) at one region of at least a first of the contact regions (first contact region). The ink is sintered or cured to remove the liquid carrier so that a substantially solid ink residue remains.