A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.

In one aspect of the semiconductor module, the sealing material on the lower side of the die stage is thinner than the sealing material on the upper side of the semiconductor element, a bent portion that forms a step with respect to vertical direction in the first lead is provided in a region sealed by the sealing material in the first lead, the side where the die stage is present of the step is positioned below the side where the die stage is not present of the step due to the step, the side where the die stage is not present of the step in the first lead protrudes from one end side of the sealing material, and a groove is provided on an upper side surface, a lower side surface, or both of them of the bent portion of the first lead.

A method comprises applying a metal-paste printing process to a surface-mount device to form a metal pillar, placing a first semiconductor die adjacent to the surface-mount device, forming a molding compound layer over the first semiconductor die and the surface-mount device, grinding the molding compound layer until a top surface of the first semiconductor die is exposed and forming a plurality of interconnect structures over the molding compound layer.

The disclosure provides a low-cost near-hermetic package, which may a substrate configured to support one or more internal components. The package may also include an enclosure comprising a cavity surrounding the one or more internal components and a first sidewall extending upward from the substrate. The first sidewall may be coupled to the substrate. The package may further include a first flexible circuit comprising conductive traces configured to connect to the one or more internal components. The first flexible circuit may include a first section outside the first sidewall of the enclosure, a second section inside the enclosure, and a third section between the first section and the second section joining to the enclosure and the substrate.

A power module includes a positive input electrode, a negative input electrode, an upper bridge substrate, a lower bridge substrate, an upper bridge chip, a lower bridge chip, an output electrode, and a signal transmission terminal stacked in sequence. The upper bridge chip has a collector connected to the upper bridge substrate, and an emitter connected to the output electrode. The lower bridge chip has a collector connected to the output electrode. A sampling terminal at the emitter of the upper bridge chip, a sampling terminal at a collector of the upper bridge chip and a control terminal of the upper bridge chip, and a sampling terminal at an emitter of the lower bridge chip, a sampling terminal at a collector of the lower bridge chip, and a control terminal of the lower bridge chip are all connected to the signal transmission terminal.

A semiconductor package includes a circuit board, an interposer structure on the circuit board, a first semiconductor chip and a second semiconductor chip on the interposer structure, the first and the second semiconductor chips electrically connected to the interposer structure and spaced apart from each other, and a mold layer between the first and second semiconductor chips, the mold layer separating the first and second semiconductor chips. A slope of a side wall of the mold layer is constant as the side wall extends away from an upper side of the interposer structure, and an angle defined by a bottom side of the mold layer and the side wall of the mold layer is less than or equal to ninety degrees.

A semiconductor package includes a bottom substrate and a top substrate space apart from the bottom substrate such that the bottom substrate and the top substrate define a gap therebetween. A logic die is mounted on a top surface of the bottom substrate. The logic die has a thickness of 125-350 micrometers. A plurality of copper cored solder balls is disposed between the bottom substrate and the top substrate around the logic die to electrically connect the bottom substrate with the top substrate. A sealing resin fills into the gap between the bottom substrate and the top substrate and sealing the logic die and the plurality of copper cored solder balls in the gap.

A package structure is provided. The package structure includes a first semiconductor package and a second semiconductor package connected to the first semiconductor package. The first semiconductor package includes an integrated circuit. The integrated circuit includes a first semiconductor die and a plurality of second semiconductor dies, the plurality of second semiconductor dies are stacked on the first semiconductor die, wherein at least one of orthogonal projections of the plurality of second semiconductor dies is partially overlapped an orthogonal projection of the first semiconductor die. The integrated circuit further includes through vias formed aside the first semiconductor and arranged in a non-overlapped region of the at least one of the orthogonal projections of the plurality of second semiconductor dies with the orthogonal projection of the first semiconductor die. A manufacturing method of a package structure is also provided.

An integrated circuit (IC) package includes one or more microelectronic devices disposed between a first side and an opposing second side of the IC package and further includes a metal frame structure comprising a metal layer disposed at the second side, an embedded ground plane (EGP) structure encircling the one or more microelectronic devices, and a set of stacked conductive structures extending from the EGP structure to the first side through a set of one or more redistribution layers at the first side. The IC package further can include an array of package contacts disposed at the first side and an encapsulant layer encapsulating the one or more microelectronic devices in a volume defined by an inner sidewall of the EGP structure.

A package structure is provided. The package structure includes a first semiconductor package and a second semiconductor package connected to the first semiconductor package. The first semiconductor package includes an integrated circuit. The integrated circuit includes a first semiconductor die and a plurality of second semiconductor dies, the plurality of second semiconductor dies are stacked on the first semiconductor die, wherein at least one of orthogonal projections of the plurality of second semiconductor dies is partially overlapped an orthogonal projection of the first semiconductor die. The integrated circuit further includes through vias formed aside the first semiconductor and arranged in a non-overlapped region of the at least one of the orthogonal projections of the plurality of second semiconductor dies with the orthogonal projection of the first semiconductor die. A manufacturing method of a package structure is also provided.