Patent classifications
H01L2924/183
Semiconductor device with a semiconductor chip connected in a flip chip manner
A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.
DOUBLE SIDE INTEGRATION SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME
An embodiment semiconductor device includes a first die package component, a second interposer electrically coupled to a first side of the first die package component, a third interposer having a voltage regulator circuit electrically coupled to a second side of the first die package component, and an optical component and a high-bandwidth-memory die, each electrically coupled to the second interposer. The first die package component may further include a double-sided semiconductor die, such that a first side of the double-sided semiconductor die is electrically coupled to the second interposer, and a second side of the double-sided semiconductor die is electrically coupled to the third interposer. The first die package component may further include a molding material and a through-molding-via formed in the molding material, such that the through-molding-via provides an electrical connection between the second interposer and the third interposer that bypasses the double-sided semiconductor die.
Packaging structures with improved adhesion and strength
According to various aspects and embodiments, a support structure for packaging an electronic device is provided. In one example, a packaged electronic device includes a substrate, at least one electronic device disposed on the substrate, an encapsulation structure disposed on the substrate and having a wall that forms a perimeter around the at least one electronic device, and at least one support structure formed from a photosensitive polymer and disposed adjacent the wall of the encapsulation structure. The at least one support structure has a configuration that provides at least one of increased adhesion and mechanical strength to the encapsulation structure.
SEMICONDUCTOR DEVICE
A semiconductor device configures one arm of an upper-lower arm circuit, and includes: a semiconductor element that includes a first main electrode and a second main electrode, wherein a main current between the first main electrode and the second main electrode; and multiple main terminals that include a first main terminal connected to the first main electrode and a second main terminal connected to the second main electrode. The first main terminal and the second main terminal are placed adjacent to each other; A lateral surface of the first main terminal and a lateral surface of the second main terminal face each other in one direction orthogonal to a thickness direction of the semiconductor element.
NO MOLD SHELF PACKAGE DESIGN AND PROCESS FLOW FOR ADVANCED PACKAGE ARCHITECTURES
Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.
SEMICONDUCTOR MODULE, AND MANUFACTURING METHOD FOR SEMICONDUCTOR MODULE
A semiconductor module includes: a first die pad having a first face, and a second face directed in a direction opposite to the first face, a first outer lead positioned in the direction in which the second face is directed relative to the first die pad, a first inner lead connecting the first die pad and the first outer lead to each other and having a stepped portion, a first semiconductor chip joined to the second face, and a sealing material sealing the first die pad and the first semiconductor chip, in which the sealing material includes a first sealing portion joined to the first face and constituted of a first resin composition, and a second sealing portion joined to the second face and constituted of a second resin composition lower in thermal conductivity than the first resin composition, and the first sealing portion has an exposed face constituting a part of an outer surface of the sealing material, a first joining face joined to the first die pad, and a second joining face joined to the stepped portion along a height direction of the stepped portion.
Semiconductor device
A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire that is bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. An area of a part of the bonding surface, the part not overlapping the wire, is small.
Seal ring designs supporting efficient die to die routing
Chip sealing designs to accommodate die-to-die communication are described. In an embodiment, a chip structure includes a split metallic seal structure including a lower metallic seal and an upper metallic seal with overlapping metallization layers, and a through seal interconnect navigating through the split metallic seal structure.
ELECTRONIC APPARATUS AND METHOD OF MANUFACTURING ELECTRONIC APPARATUS
According to an embodiment, an electronic apparatus includes a substrate, a semiconductor device, a non-conductive portion, first and second metal films, and a rechargeable battery. The semiconductor device is mounted on a first surface of the substrate and includes a wireless circuit. The non-conductive portion is formed on the first surface to seal the semiconductor device. The first metal film is provided along a surface of the non-conductive portion and at least one edge surface of the substrate to contact at the edge surface with a first-wire disposed on the substrate. The second metal film is provided along the surface of the non-conductive portion and the edge surface and separately from the first metal film to contact at the edge surface with a second-wire disposed on the substrate. The rechargeable battery includes first and second electrodes electrically connected to the first-wire and to the second-wire, respectively.
SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR CHIP CONNECTED IN A FLIP CHIP MANNER
A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.