A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.

To provide a thin film capacitor in which peeling-off of an electrode layer is less likely to occur. A thin film capacitor includes a metal foil having a roughened upper surface, a dielectric film covering the upper surface of the metal foil and having an opening for partly exposing the metal foil therethrough, a first electrode layer contacting the metal foil through the opening and further contacting the dielectric film, and a second electrode layer contacting the dielectric film without contacting the metal foil. With this configuration, both the first and second electrode layers can be disposed on the upper surface of the metal foil. In addition, the first electrode layer contacts not only the metal foil but also the dielectric film, making peeling of the first electrode layer less likely to occur.

To provide a thin film capacitor having high adhesion with respect to a circuit substrate. A thin film capacitor includes: a metal foil having a roughened upper surface; a dielectric film covering the upper surface of the metal foil and having an opening through which the metal foil is partly exposed; a first electrode layer contacting the metal foil through the opening; and a second electrode layer contacting the dielectric film without contacting the metal foil. An angle θa formed by the other main surface of the metal foil and a side surface thereof is more than 20° and less than 80°. The side surface is thus tapered at an angle of more than 20° and less than 80°, so that it is possible to suppress warpage and to enhance adhesion with respect to a multilayer substrate when the thin film capacitor is embedded in the multilayer substrate.

A thin film capacitor includes: a metal foil having a roughened upper surface; a dielectric film covering the upper surface of the metal foil and having an opening through which the metal foil is partly exposed; a first electrode layer contacting the metal foil through the opening; a second electrode layer contacting the dielectric film without contacting the metal foil; and an insulating member separating the first and second electrode layers. The insulating member has a tapered shape in cross section. With the above configuration, both the first and second electrode layers can be disposed on the upper surface of the metal foil. In addition, since the insulating member has a tapered shape in cross section, adhesion performance of the insulating member can be enhanced, thus making it possible to prevent short-circuit between the first and second electrode layers.

To provide a thin film capacitor in which warpage is less likely to occur. A thin film capacitor includes: a metal foil having roughened upper and lower surfaces; a dielectric film covering the upper surface of the metal foil and having an opening through which the metal foil is partly exposed; a dielectric film covering the lower surface of the metal foil and made of a dielectric material having a thermal expansion coefficient smaller than that of the metal foil; a first electrode layer contacting the metal foil through the opening; and a second electrode layer contacting the first dielectric film without contacting the metal foil. The lower surface of the metal foil is thus covered with the dielectric film having a small thermal expansion coefficient, thereby making it possible to prevent the occurrence of warpage.

To provide a thin film capacitor having high adhesion performance with respect to a circuit substrate. A thin film capacitor includes: a metal foil having a roughened upper surface; a dielectric film covering the upper surface of the metal foil and having an opening through which the metal foil is partly exposed; a first electrode layer contacting the metal foil through the opening; and a second electrode layer contacting the dielectric film without contacting the metal foil. The first and second electrode layers are formed in an area surrounded by an outer peripheral area of the upper surface of the metal foil so as not to cover the outer peripheral area. The outer peripheral area of the roughened upper surface of the metal foil is thus exposed, so that adhesion performance with respect to a circuit substrate can be enhanced.

To provide a thin film capacitor in which a pair of terminal electrodes can be disposed on the same plane. A thin film capacitor includes a metal foil having a roughened upper surface, a dielectric film covering the upper surface of the metal foil and having an opening for partly exposing the metal foil therethrough, a first electrode layer contacting the metal foil through the opening, and a second electrode layer contacting the dielectric film without contacting the metal foil. With this configuration, both the first and second electrode layers can be disposed on the upper surface of the metal foil. In addition, since the metal foil is surface-roughened, a larger capacitance can be obtained.

To provide a thin film capacitor having high flexibility. A thin film capacitor includes: a metal foil having a roughened upper surface; a dielectric film covering the upper surface of the metal foil and having an opening through which the metal foil is partly exposed; a first electrode layer contacting the metal foil through the opening; and a second electrode layer contacting the dielectric film without contacting the metal foil. The particle diameter of crystal at a non-roughened center part of the metal foil is less than 15 μm in the planar direction and less than 5 μm in the thickness direction. This can not only enhance the flexibility of the metal foil to reduce a short-circuit failure in a state where the thin film capacitor is incorporated in a multilayer substrate but also enhance positional accuracy.

A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.

A semiconductor device includes: a wiring board including first to third bonding pads; a chip stack including semiconductor chips, each chip having first to third connection pads, the first connection pads being connected in series to each other and to the first bonding pad through first bonding wires to form a first transmission channel, the second connection pads being connected in series to each other and to the second bonding pad through second bonding wires to form a second transmission channel, and the third connection pads being connected in series to each other and to the third bonding pad through third bonding wires to form a third transmission channel; and at least one of a first and a second terminating resistor being provided above the chip stack, the first resistor being connected to the first and second channels, the second resistor being connected to the first and third channels.