A method includes measuring a first calibration kit in a wafer to obtain a first performance data. The wafer includes a substrate, and a plurality of dielectric layers over the substrate. The first calibration kit includes a first passive device over the plurality of dielectric layers, wherein substantially no metal feature is disposed in the plurality of dielectric layers and overlapped by the first passive device. The method further includes measuring a second calibration kit in the wafer to obtain a second performance data. The second calibration kit includes a second passive device identical to the first device and over the plurality of dielectric layers, and dummy patterns in the plurality of dielectric layers and overlapped by the second passive device. The first performance data and the second performance data are de-embedded to determine an effect of metal patterns in the plurality of dielectric layers to overlying passive devices.

A semiconductor device includes a first plurality of dies encapsulated by an encapsulant, an interposer over the first plurality of dies, an interconnect structure over and electrically connected to the interposer, and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. The interposer includes a plurality of embedded passive components. Each die of the first plurality of dies is electrically connected to the interposer. The interconnect structure includes a solenoid inductor in a metallization layer of the interconnect structure.

According to one embodiment, a semiconductor photo-receiving device includes a substrate, a light propagation layer and a semiconductor layer including a lowest layer and upper layers. The upper layers include an optical absorption layer. The light propagation layer includes a first light input layer, a first annular layer at a desired distance from the first light input layer, and a first optical waveguide connecting the first light input layer and annular layer. The lowest layer of the semiconductor layer includes a second light input layer, a second annular layer at a desired distance from the second light input layer, and a second optical waveguide connecting the second light input layer and annular layer.

According to one embodiment, a semiconductor photo-receiving device includes a substrate, a light propagation layer and a semiconductor layer including a lowest layer and upper layers. The upper layers include an optical absorption layer. The light propagation layer includes a first light input layer, a first annular layer at a desired distance from the first light input layer, and a first optical waveguide connecting the first light input layer and annular layer. The lowest layer of the semiconductor layer includes a second light input layer, a second annular layer at a desired distance from the second light input layer, and a second optical waveguide connecting the second light input layer and annular layer.

An electrical circuit device includes a circuit board including a cavity extending from a top surface of the circuit board to an embedded conductor, an integrated circuit chip in the cavity, an electrical connection between the integrated circuit chip and the embedded conductor, a thermal slug disposed over a top surface of the integrated circuit chip, and a heat sink mounted to an outer surface of the thermal slug for transferring a thermal energy away from the circuit board, the heat sink extending above a top surface of the circuit board.

A method of mounting an integrated circuit chip to a circuit board includes placing the integrated circuit chip into a cavity extending from a surface of the circuit board to an embedded conductor, and electrically connecting the integrated circuit chip to the embedded conductor.

An electrical circuit device that includes a circuit board with an integrated circuit chip in a cavity that extends from a surface of the circuit board to an embedded conductor, and an electrical connection between the integrated circuit chip and the embedded conductor.

A millimeter-wave dielectric transmission device. The millimeter-wave dielectric transmission device includes a semiconductor chip provided on one interposer substrate and capable of millimeter-wave dielectric transmission, an antenna structure connected to the semiconductor chip, two semiconductor packages including a molded resin configured to cover the semiconductor chip and the antenna structure, and a dielectric transmission path provided between the two semiconductor packages to transmit a millimeter wave signal. The semiconductor packages are mounted such that the antenna structures thereof are arranged with the dielectric transmission path interposed therebetween.

Shielding of high-frequency circuits is achieved using a simple and inexpensive configuration not using any lid. A high-frequency circuit mounting substrate (20) is disposed, on an underside surface layer of which are disposed high-frequency circuits (21 and 22) and is formed a first grounding conductor that has same electric potential as grounding conductors of the high-frequency circuits and that surrounds the high-frequency circuits. A mother control substrate (3) is disposed, on which the high-frequency circuit mounting substrate (20) is mounted in such a way that the high-frequency circuits are sandwiched therebetween and on which a second grounding conductor is formed in a region facing the high-frequency circuits. Plural first lands are formed on the first grounding conductor of the high-frequency circuit mounting substrate (20) to surround the high-frequency circuits. Plural second lands are formed that are electrically connected to the second grounding conductor at positions on a surface layer of the mother control substrate (3) which face the first lands. Plural solder balls (30G2) are disposed for connecting the first lands and the second lands. The high-frequency circuits are housed in pseudo shielding cavities surrounded by the solder balls (30G2), the grounding conductors of the high-frequency circuits, and the first and second grounding conductors.

The invention provides a semiconductor structure, which comprises a first chip and a second chip attached to each other, wherein the first chip comprises a quantum dot pattern, and the second chip comprises a through silicon via (TSV), wherein the quantum dot pattern and the through silicon via are aligned with each other.