A structure with controlled capillary coverage is provided and includes a substrate including one or more first contacts, a component and adhesive. The component includes one or more second contacts and a rib disposed at a distance from each of the one or more second contacts. The component is disposed such that the one or more second contacts are communicative with the one or more first contacts and corresponding surfaces of the substrate and the rib face each other at a controlled gap height to define a fill-space. The adhesive is dispensed at a discrete point whereby the adhesive is drawn to fill the fill-space by capillary action.

A package comprising a substrate, a first antenna device, and an integrated device. The substrate comprising a first surface and a second surface, where the substrate comprises a plurality of interconnects. The first antenna device is coupled to the first surface of the substrate, through a first plurality of solder interconnects. The integrated device is coupled to the second surface of the substrate. The package may include an encapsulation layer located over the second surface of the substrate, where the encapsulation layer encapsulates the integrated device. The package may include a shield formed over a surface of the encapsulation layer, where the shield includes an electromagnetic interference (EMI) shield.

Chip package structure and chip package method are provided. The chip package structure includes an encapsulating layer, a redistribution layer, a soldering pad group, and bare chips. Connecting posts is formed on a side of the bare chips. The encapsulating layer covers the bare chips and the connecting posts, while exposes a side of the connecting posts away from the bare chips. The redistribution layer on the connecting posts includes a first redistribution wire, a second redistribution wire, and a third redistribution wire. The first redistribution wire and the second redistribution wire are electrically connected to at least one connecting post respectively, and the third redistribution layer is electrically connected to remaining connecting posts. The soldering pad group on the redistribution layer includes an input soldering pad electrically connected to the first redistribution wire and an output soldering pad electrically connected to the second redistribution wire.

Provided is a circuit board including: a metal core layer having a first main surface capable of supporting a mounting component and a second main surface which is opposite to the first main surface; a first exterior coating base material which is arranged facing the first main surface; and a second exterior coating base material which is arranged facing the second main surface and includes a heat dissipation layer having a via which is connected to the second main surface.

An apparatus includes an antenna array package cover comprising a radiating surface, a mating surface disposed opposite the radiating surface, and an array of antenna array sub-patterns wherein each antenna array sub-pattern comprises at least one antenna element. The antenna array package also includes an array of sub-pattern interface packages mated to the mating surface of the antenna array package cover. Each sub-pattern interface package of the array of sub-pattern interface packages comprises a package carrier, a sub-pattern integrated circuit electrically and mechanically coupled to the package carrier, and a set of interface lines corresponding to the antenna elements of the antenna array sub-pattern that corresponds to the sub-pattern interface package. Methods for mounting the above apparatus into a host circuit are also disclosed herein.

Embodiments include a microelectronic package structure having a substrate with one or more substrate pads on a first side of the package substrate. A ball interconnect structure is on the substrate pad, the ball interconnect structure comprising at least 99.0 percent gold. A discrete component having two or more component terminals is on the ball interconnect structure.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a radio frequency (RF) die having a lateral surface area and a plurality of contacts on a face, where the RF die is embedded in the package substrate with the plurality of contacts facing towards the second surface of the package substrate, and an RF front end between the RF die and the first surface of the package substrate, where the RF front end is positioned under the RF die and does not extend beyond the lateral surface area of the RF die.

Methods of producing a fan-out wafer level package and the resulting device are provided. Embodiments include forming vias in a first surface of a carrier wafer; filling the vias with a metal; forming a redistribution layer (RDL) over the carrier wafer, the RDL being in contact with the metal filled vias; attaching a semiconductor die to the RDL; forming a wafer mold over the semiconductor die; and removing a portion of the carrier wafer to expose the metal filled vias on a second surface of the carrier wafer.

A semiconductor package includes a die pad, a semiconductor die mounted on the die pad, rows of terminal leads disposed around the die pad; a surface mount device (SMD) mounted and bonded with a bond wire in the semiconductor package; and a molding compound encapsulating the semiconductor die and the SMD, the bond wire, and at least partially encapsulating the die pad and the terminal leads. The SMD may be mounted in the semiconductor package by using a non-conductive paste or a conductive paste. The die pad, the tie bars and the terminal leads are coplanar.

An electrical component and method for manufacturing the electrical component with a substrate a conductor stack having multiple layers and including at least one electrically conductive path. The conductor stack mounted to the substrate with a dielectric passivation stack encasing at least a portion of the conductor stack.