A semiconductor package (1, 1, 1), the package (1, 1, 1) comprising a first substrate (2) comprising at a front cavity side (5) a plurality of cavities (6, 6), each of the cavities (6, 6) having a bottom wall (7) and side walls (8), and having a conductive path (10) forming an electric contact surface (9) located at the inner side of the bottom wall (7) of the cavity (6, 6), a plurality of semiconductor elements (16, 7), each of the semiconductor elements (16, 17) comprising a first electric contact surface (9) on a first side (26) and a second electric contact surface (9) on a second side (28) opposite to the first side (26), wherein at least one of the semiconductor elements (16, 17) is placed within a corresponding cavity (6, 6) at the front cavity side (5) of the first substrate (2), wherein the first electric contact (27) of the semiconductor element (16, 17) and the electric contact surface (9) at the inner side of the bottom wall (7) of the corresponding cavity (6, 6) are electrically conductive bonded in a material-locking manner, and a second substrate (3), the second substrate (3) being attached with a connection side (12, 13) to the front cavity side (5) of the first substrate (2) thereby encapsulating the semiconductor elements (16, 17) located within the corresponding cavities (6, 6) at the front cavity side (5) of the first substrate (2).

A memory package includes a multi-level package substrate, a first memory chip, a second memory chip, a first band pass filter and a second band pass filter. The multi-level package substrate includes a plurality of wiring layers and a plurality of insulating layers alternately stacked on one another. The first memory chip is on the multi-level package substrate, and includes a plurality of first memory cells and a first receiver. The second memory chip is on the first memory chip, and includes a plurality of second memory cells and a second receiver. The first band pass filter is in the multi-level package substrate, is connected to the first receiver, and passes a first data signal within a first frequency band. The second band pass filter is in the multi-level package substrate, is connected to the second receiver, and passes a second data signal within the first frequency band.

The embodiments described herein provide radio frequency (RF) amplifiers, and in some embodiments provide amplifiers that can be used in high power RF applications. Specifically, the amplifiers described herein may be implemented to include one or more matching networks with the transistor(s) and inside the device package in a way that may facilitate operation at high frequencies and over wide bandwidths. Specifically, the amplifiers can be implemented with matching networks that include inductive and capacitive elements arranged in double T-match configuration, where at least some inductive elements are implemented with bond wires and the capacitive elements are implemented with integrated passive devices (IPDs). In such implementations the double T-match configuration of the matching network can be fully implemented inside the package, and may provide the amplifier with high frequency, wide bandwidth performance.

Disclosed is a package for a semiconductor device including a semiconductor die. The package includes a base member, a side wall, first and second conductive films, and first and second conductive leads. The base member has a conductive main surface including a region that mounts the semiconductor die. The side wall surrounds the region and is made of a dielectric. The side wall includes first and second portions. The first and second conductive films are provided on the first and second portions, respectively and are electrically connected to the semiconductor die. The first and second conductive leads are conductively bonded to the first and second conductive films, respectively. At least one of the first and second portions includes a recess in its back surface facing the base member, and the recess defines a gap between the at least one of the first and second portions below the corresponding conductive film and the base member.

An RF flip chip is provided in which a local bump region adjacent a die corner includes a balun having a centrally-located bump.

Apparatus implementing various structures to decrease the distance between two inductive elements for tuning an inductance with greater variability (a wider tuning range). One example integrated circuit (IC) package generally includes a laminate, a solder resist layer disposed on an upper surface of the laminate, and a semiconductor die disposed above the laminate and comprising a first inductor. At least a portion of a second inductor is disposed above a section of the solder resist layer, the first inductor at least partially overlaps the second inductor, and there is a gap between the first inductor and the second inductor.

The present disclosure relates to a radio frequency (RF) power transistor package. It further relates to a mobile telecommunications base station comprising such an RF power transistor package, and to an integrated passive die suitable for use in an RF power amplifier package. In example embodiments, an in-package impedance network is used that is connected to an output of the RF power transistor arranged inside the package. This network comprises a first inductive element having a first and second terminal, the first terminal being electrically connected to the output of the RF transistor, a resonance unit electrically connected to the second terminal of the first inductive element, and a second capacitive element electrically connected in between the resonance unit and ground, where the first capacitive element is arranged in series with the second capacitive element.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a radio frequency (RF) die having a lateral surface area and a plurality of contacts on a face, where the RF die is embedded in the package substrate with the plurality of contacts facing towards the second surface of the package substrate, and an RF front end between the RF die and the first surface of the package substrate, where the RF front end is positioned under the RF die and does not extend beyond the lateral surface area of the RF die.

A memory package includes a multi-level package substrate, a first memory chip, a second memory chip, a first band pass filter and a second band pass filter. The multi-level package substrate includes a plurality of wiring layers and a plurality of insulating layers alternately stacked on one another. The first memory chip is on the multi-level package substrate, and includes a plurality of first memory cells and a first receiver. The second memory chip is on the first memory chip, and includes a plurality of second memory cells and a second receiver. The first band pass filter is in the multi-level package substrate, is connected to the first receiver, and passes a first data signal within a first frequency band. The second band pass filter is in the multi-level package substrate, is connected to the second receiver, and passes a second data signal within the first frequency band.

The present disclosure relates to a radio frequency (RF) power transistor package. It further relates to a mobile telecommunications base station comprising such an RF power transistor package, and to an integrated passive die suitable for use in an RF power amplifier package. In example embodiments, an in-package impedance network is used that is connected to an output of the RF power transistor arranged inside the package. This network comprises a first inductive element having a first and second terminal, the first terminal being electrically connected to the output of the RF transistor, a resonance unit electrically connected to the second terminal of the first inductive element, and a second capacitive element electrically connected in between the resonance unit and ground, where the first capacitive element is arranged in series with the second capacitive element.