Provided is a bonding wire capable of reducing the occurrence of defective loops. The bonding wire includes: a core material which contains more than 50 mol % of a metal M; an intermediate layer which is formed over the surface of the core material and made of Ni, Pd, the metal M, and unavoidable impurities, and in which the concentration of the Ni is 15 to 80 mol %; and a coating layer formed over the intermediate layer and made of Ni, Pd and unavoidable impurities. The concentration of the Pd in the coating layer is 50 to 100 mol %. The metal M is Cu or Ag, and the concentration of Ni in the coating layer is lower than the concentration of Ni in the intermediate layer.

Provided is a bonding wire capable of reducing the occurrence of defective loops. The bonding wire includes: a core material which contains more than 50 mol % of a metal M; an intermediate layer which is formed over the surface of the core material and made of Ni, Pd, the metal M, and unavoidable impurities, and in which the concentration of the Ni is 15 to 80 mol %; and a coating layer formed over the intermediate layer and made of Ni, Pd and unavoidable impurities. The concentration of the Pd in the coating layer is 50 to 100 mol %. The metal M is Cu or Ag, and the concentration of Ni in the coating layer is lower than the concentration of Ni in the intermediate layer.

A solder paste that contains or consists of (i) 10-30% by weight of at least one type of particles that each contain a phosphorus fraction of >0 to ≦500 wt-ppm and are selected from copper particles, copper-rich copper/zinc alloy particles, and copper-rich copper/tin alloy particles, (ii) 60-80% by weight of at least one type of particles selected from tin particles, tin-rich tin/copper alloy particles, tin-rich tin/silver alloy particles, and tin-rich tin/copper/silver alloy particles, and (iii) 3-30% by weight solder flux, in which the mean particle diameter of metallic particles (i) and (ii) is ≦15 μm.

A package structure and a method for connecting components are provided, in which the package includes a first substrate including a first wiring and at least one first contact connecting to the first wiring; a second substrate including a second wiring and at least one second contact connecting to the second wiring, the at least one first contact and the at least one second contact partially physically contacting with each other or partially chemically interface reactive contacting with each other; and at least one third contact surrounding the at least one first contact and the at least one second contact. The first substrate and the second substrate are electrically connected with each other at least through the at least one first contact and the at least one second contact.

A method for disassembling a stack of at least three substrates. The invention relates to the techniques for transferring thin films in the microelectronics field. It proposes a method for disassembling a stack of at least three substrates having between them two interfaces, one interface of which has an adhesion energy and an interface of which has an adhesion energy, with less than, the method comprising: 1) implementing a removal of material on the first substrate, in order to expose a surface of the second substrate, 2) transferring the stack onto a flexible adhesive film so that the surface has, with an adhesive layer of the film, an adhesion energy greater than, and 3) disassembling the third substrate at the interface between the second substrate and the third substrate. The method makes it possible to open the stack via the interface thereof with the highest adhesion energy.

A method includes filling a trench formed in a first integrated circuit carrier with temporary bonding material to form a temporary bonding layer. At least one chip is bonded over the temporary bonding layer.

The present disclosure relates to an Ag paste composition and a bonding film produced using same, the Ag paste composition being coated on a first object, and the first object being pressure sintered toward a second object side, thereby forming a sintered bonding layer between the first object and the second object, wherein the Ag paste composition comprises 90˜99 wt % of Ag powder, and 1˜10 wt % of an organic binder. The present disclosure controls the specific surface area and grain shape of the Ag powder, even without applying a spherical nanoparticle powder, and thus has the advantages of lowering a bond temperature and increasing bond density, thereby enabling the improvement of bond strength and reliability.

A method of designing a layout includes determining a first layout pattern, wherein the first layout pattern corresponds to a plurality of contact pads. The method further includes generating a second layout pattern. The method further includes checking whether an edge of the second layout pattern overlaps the first layout pattern. The method further includes adjusting the second layout pattern so that the edge of the second layout pattern overlaps the first layout pattern in response to a determination that the edge of the second layout pattern is separated from the first layout pattern.

In an embodiment, a device includes: a dielectric layer over an active surface of a semiconductor substrate; a conductive via in the dielectric layer, the conductive via including a first copper layer having a non-uniform grain orientation; and a bonding pad over the conductive via and in the dielectric layer, the bonding pad including a second copper layer having a uniform grain orientation, a top surface of the bonding pad being coplanar with a top surface of the dielectric layer.

When a semiconductor unit is heated, a heater having a flat heating surface is used for performing heating in a state in which a lower surface of an insulated circuit board is placed on the heating surface. When the semiconductor unit is cooled, a cooler having a cooling surface including a pair of support portions is used for performing cooling in which a lower surface of a pair of outer regions of the insulated circuit board are respectively placed to be contact with the pair of support portions, and in which a central region between the pair of outer regions of the insulated circuit board is pressed downward so as to be downward convex.