A bonding wire includes a Cu alloy core material, and a Pd coating layer formed on the Cu alloy core material. The bonding wire contains at least one element selected from Ni, Zn, Rh, In, Ir, and Pt. A concentration of the elements in total relative to the entire wire is 0.03% by mass or more and 2% by mass or less. When measuring crystal orientations on a cross-section of the core material in a direction perpendicular to a wire axis of the bonding wire, a crystal orientation <100> angled at 15 degrees or less to a wire axis direction has a proportion of 50% or more among crystal orientations in the wire axis direction. An average crystal grain size in the cross-section of the core material in the direction perpendicular to the wire axis of the bonding wire is 0.9 m or more and 1.3 m or less.

A method includes forming a dielectric layer over a carrier, forming a plurality of bond pads in the dielectric layer, and performing a planarization to level top surfaces of the dielectric layer and the plurality of bond pads with each other. A device die is bonded to the dielectric layer and portions of the plurality of bond pads through hybrid bonding. The device die is encapsulated in an encapsulating material. The carrier is then demounted from the device die and the dielectric layer.

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer on a surface of the Cu alloy core material, and contains Ga and Ge of 0.011 to 1.2% by mass in total, which is able to increase bonding longevity of the ball bonded part in the high-temperature, high-humidity environment, and thus to improve the bonding reliability. The thickness of the Pd coating layer is preferably 0.015 to 0.150 m. When the bonding wire further contains one or more elements of Ni, Ir, and Pt in an amount, for each element, of 0.011 to 1.2% by mass, it is able to improve the reliability of the ball bonded part in a high-temperature environment at 175 C. or more. When an alloy skin layer containing Au and Pd is further formed on a surface of the Pd coating layer, wedge bondability improves.

A bonding wire for a semiconductor device includes a Cu alloy core material and a Pd coating layer on a surface of the Cu alloy core material, and contains Ga and Ge of 0.011 to 1.2% by mass in total, which is able to increase bonding longevity of the ball bonded part in the high-temperature, high-humidity environment, and thus to improve the bonding reliability. The thickness of the Pd coating layer is preferably 0.015 to 0.150 m. When the bonding wire further contains one or more elements of Ni, Ir, and Pt in an amount, for each element, of 0.011 to 1.2% by mass, it is able to improve the reliability of the ball bonded part in a high-temperature environment at 175 C. or more. When an alloy skin layer containing Au and Pd is further formed on a surface of the Pd coating layer, wedge bondability improves.

A method of fabricating a semiconductor device includes forming a first contact pad and a second contact pad over a first passivation layer, depositing a first buffer layer over the first contact pad and the second contact pad, and depositing a second buffer layer over the first buffer layer and the second contact pad. The first contact pad is in a circuit region and the second contact pad is in a non-circuit region. An edge of the second contact pad is exposed and a periphery of the first contact pad and an edge of the second contact pad are covered by the first buffer layer.

A method of bonding two different substances includes the steps of: applying a bonding material containing a flux component that includes an organic material having at least two carboxyl groups to a bonding surface of a bonding object, disposing an object to be bonded on the bonding material, performing preliminary firing at a preset temperature in a state in which the object to be bonded is disposed, and performing a main firing by heating at a temperature higher than the temperature of the preliminary firing.

A hybrid bonded structure including a first integrated circuit component and a second integrated circuit component is provided. The first integrated circuit component includes a first dielectric layer, first conductors and isolation structures. The first conductors and the isolation structures are embedded in the first dielectric layer. The isolation structures are electrically insulated from the first conductors and surround the first conductors. The second integrated circuit component includes a second dielectric layer and second conductors. The second conductors are embedded in the second dielectric layer. The first dielectric layer is bonded to the second dielectric layer and the first conductors are bonded to the second conductors.

A sintering powder comprising: a first type of metal particles having a mean longest dimension of from 100 nm to 50 ?m.

A semiconductor component support is provided which includes a component support portion for a semiconductor component to be mounted on the semiconductor component support portion. The component support portion includes a metal part that includes an opening in plan view. The opening of the metal part includes first and second sections. The second section communicates with the first section, and is arranged outside the first section. The second section is wider than the first section. The first section can be at least partially positioned directly under a mount-side main surface of the semiconductor component.

An embodiment of the invention may include a semiconductor structure, and method of forming the semiconductor structure. The semiconductor structure may include a first set of pillars located on a first substrate. The semiconductor structure may include a second set of pillars located on a second substrate. The semiconductor structure may include a joining layer connecting the first pillar to the second pillar. The semiconductor structure may include an underfill layer located between the first and second substrate.