A dual sided molded package has a substrate with pads of varying size configured to receive electrically conductive interconnect members thereon. The pads include first pads that have a larger surface area than a surface area of second pads. In one implementation, one or more first pads are proximate the corners of the substrate. First interconnect members are attached to the first pads and second interconnect members are attached to the second pads. The first interconnect members have an exposed solderable area that is substantially equal to the surface area of the first pads, and the second interconnect members have an exposed solderable area that is substantially equal to the surface area of the second pads. The first exposed solderable area is larger than the second exposed solderable area.

A dual sided molded package has a substrate with pads of varying size configured to receive electrically conductive interconnect members thereon. The pads include first pads that have a larger surface area than a surface area of second pads. In one implementation, one or more first pads are proximate the corners of the substrate. First interconnect members are attached to the first pads and second interconnect members are attached to the second pads. The first interconnect members have an exposed solderable area that is smaller than the surface area of the first pads, and the second interconnect members have an exposed solderable area that is substantially equal to the surface area of the second pads. The first exposed solderable area is substantially equal to the second exposed solderable area.

Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, and a die coupled to the package substrate. In an embodiment, a stiffener is around the die and over the package substrate. In an embodiment, an electrically non-conductive underfill is around first level interconnects (FLIs) between the package substrate and the die. In an embodiment, an electrically conductive layer is around the non-conductive underfill.

An electronic package is provided, in which a plurality of antenna structures and a heat sink are integrated on a package module including an electronic element, so as to guide the heat energy generated by the electronic element out of the package module via the heat sink. Therefore, when the electronic package is configured with the plurality of antenna structures, the heat dissipation of the electronic element can be improved.

An electronic package is provided, in which a package module and a shielding member are disposed on a carrier structure, such that the shielding member covers a top surface and side surfaces of the package module to block the radiation outward from the package module and prevent problem that other electronic components on the carrier structure cannot be transmitted signals normally due to the electromagnetic interference of the package module.

IC device package routing with metallization features comprising a pseudo-stripline architecture in which the stripline structure is provisioned, in part, by a routing structure separate from routing within the package substrate. A signal route within top metallization level of a package substrate may be electrically shielded, in part, with a metallization feature within a redistribution layer (RDL) of a routing structure that couples one or more IC chips to the package substrate. Accordingly, a package substrate may have fewer levels of metallization, reduced thickness, and/or lower cost while the IC device package still offers excellent EMI performance.

A semiconductor device has an antenna substrate and a component module disposed over the antenna substrate. The component module includes an electrical component, and a conductive structure formed around the electrical component. Alternatively, an electrical component can be disposed over the antenna substrate, and a conductive structure is disposed over the antenna substrate and around the electrical component. An encapsulant is deposited around the electrical component and conductive structure. A shielding material is formed over the component module, and a heat sink formed over the component module. The shielding material can be formed over the component module, while the heat sink is formed over the shielding material. Alternatively, the heat sink is formed over the component module, while the shielding material is formed over the heat sink. The conductive structure has a plurality of posts or a frame. A thermal interface material is disposed over the component module.

A module is described. The module includes two dies which are stacked over a top insulating layer of a PCB. When both dies are be connected to the PCB through a copper pillar, the top die has a taller interconnect and the bottom die has a shorter interconnect. To further reduce a height of the module, the bottom die and/or the top die may be placed into a cavity of the PCB and a bulk silicon layer of the top die may be grinded away.

The present disclosure provides an electronic device. The electronic device includes a first interposer, a first interconnection array, a first shielding wall, and a second interconnection array. The first interconnection array is disposed in the first interposer and electrically connected to ground. The first shielding wall continuously extends at a side of the first interconnection array. The second interconnection array is disposed between the first shielding wall and the first interconnection array. The second interconnection array is configured to transmit a signal.

In a described example, an apparatus includes: a semiconductor device mounted to a device side surface of a package substrate, the package substrate having a board side surface opposite the device side surface; an antenna module mounted to the package substrate and coupled to the semiconductor device; and mold compound covering the semiconductor device and a portion of the package substrate.