A manufacturing method of a semiconductor device includes sealing a metal plate on which a semiconductor chip and a control IC are mounted by injecting molding resin raw material into a cavity from an inlet, filling the cavity with the molding resin raw material, and discharging excessive molding resin raw material from an outlet. In the case of the semiconductor device manufactured in this way, at least, generation of voids is reduced in an area around the semiconductor chip and the control IC. Thus, occurrence of an electrical discharge in the semiconductor device is reduced, and deterioration of the reliability of the semiconductor device is prevented.

A method including stacking a number of silicon dice such that one or more edges of the dice are in vertical alignment, where the one or more edges include a number of connection pads. The method also includes positioning a connecting wire on a substantially perpendicular axis to the one or more edges. The connecting wire includes a number of solder blocks formed thereon. The solder blocks are spaced at intervals associated with a distance between a first set of aligned connection pads on the dice. The connecting wire is positioned such that the solder blocks are in contact with the first set of aligned connection pads. The method also includes applying heat to cause the solder blocks to reflow and physically and electrically couple the connecting wire to the connection pads.

A method including stacking a number of silicon dice such that one or more edges of the dice are in vertical alignment, where the one or more edges include a number of connection pads. The method also includes positioning a connecting wire on a substantially perpendicular axis to the one or more edges. The connecting wire includes a number of solder blocks formed thereon. The solder blocks are spaced at intervals associated with a distance between a first set of aligned connection pads on the dice. The connecting wire is positioned such that the solder blocks are in contact with the first set of aligned connection pads. The method also includes applying heat to cause the solder blocks to reflow and physically and electrically couple the connecting wire to the connection pads.

There is provided a palladium-coated copper bonding wire that does not cause a shrinkage cavity during first bonding, has high bonding reliability, and is capable of maintaining excellent bonding reliability for a long period of time even in high-temperature and high-humidity environments. A palladium-coated copper bonding wire in which a concentration of palladium is 1.0 mass % or more and 4.0 mass % or less relative to the total of copper, palladium, and a sulfur group element, a total concentration of the sulfur group element is 50 mass ppm or less, and a concentration of sulfur is 5 mass ppm or more and 12 mass ppm or less, a concentration of selenium is 5 mass ppm or more and 20 mass ppm or less, or a concentration of tellurium is 15 mass ppm or more and 50 mass ppm or less, and the palladium-coated copper bonding wire including a palladium-concentrated region with the average concentration of palladium of 6.5 atom % or more and 30.0 atom % or less relative to the total of copper and palladium within a range from a surface of a tip portion of a free air ball formed at a tip of the wire to 5.0 nm or more and 100.0 nm or less.

There is provided a palladium-coated copper bonding wire that does not cause a shrinkage cavity during first bonding, has high bonding reliability, and is capable of maintaining excellent bonding reliability for a long period of time even in high-temperature and high-humidity environments. A palladium-coated copper bonding wire in which a concentration of palladium is 1.0 mass % or more and 4.0 mass % or less relative to the total of copper, palladium, and a sulfur group element, a total concentration of the sulfur group element is 50 mass ppm or less, and a concentration of sulfur is 5 mass ppm or more and 12 mass ppm or less, a concentration of selenium is 5 mass ppm or more and 20 mass ppm or less, or a concentration of tellurium is 15 mass ppm or more and 50 mass ppm or less, and the palladium-coated copper bonding wire including a palladium-concentrated region with the average concentration of palladium of 6.5 atom % or more and 30.0 atom % or less relative to the total of copper and palladium within a range from a surface of a tip portion of a free air ball formed at a tip of the wire to 5.0 nm or more and 100.0 nm or less.

A microelectronic package includes at least two semiconductor die, one die stacked over at least partially another. At a least the upper die is oriented with its active surface facing in the direction of a redistribution structure, and one or more wires are coupled to extend from contacts on that active surface into conductive structures in the redistribution structure.

A microelectronic package includes at least two semiconductor die, one die stacked over at least partially another. At a least the upper die is oriented with its active surface facing in the direction of a redistribution structure, and one or more wires are coupled to extend from contacts on that active surface into conductive structures in the redistribution structure.

A semiconductor device includes a single lead frame, a semiconductor element, and a mold material. The semiconductor element is joined onto one main surface of the lead frame. The lead frame includes a die-attach portion, a signal terminal portion, and a ground terminal portion. The die-attach portion, the signal terminal portion, and the ground terminal portion are disposed directly below the mold material so as to be arranged in a direction along one main surface. A groove portion is provided by partially removing the lead frame so as to allow the groove portion to pass therethrough, the groove portion being provided between the die-attach portion and the ground terminal portion adjacent to each other in the lead frame and between the signal terminal portion and the ground terminal portion adjacent to each other in the lead frame.

A semiconductor device includes a single lead frame, a semiconductor element, and a mold material. The semiconductor element is joined onto one main surface of the lead frame. The lead frame includes a die-attach portion, a signal terminal portion, and a ground terminal portion. The die-attach portion, the signal terminal portion, and the ground terminal portion are disposed directly below the mold material so as to be arranged in a direction along one main surface. A groove portion is provided by partially removing the lead frame so as to allow the groove portion to pass therethrough, the groove portion being provided between the die-attach portion and the ground terminal portion adjacent to each other in the lead frame and between the signal terminal portion and the ground terminal portion adjacent to each other in the lead frame.

A wire comprising a wire core with a surface, the wire core having a coating layer superimposed on its surface, wherein the wire core itself consists of: (a) pure silver consisting of (a1) silver in an amount in the range of from 99.99 to 100 wt.-% and (a2) further components in a total amount of from 0 to 100 wt.-ppm or (b) doped silver consisting of (b1) silver in an amount in the range of from >99.49 to 99.997 wt.-%, (b2) at least one doping element selected from the group consisting of calcium, nickel, platinum, palladium, gold, copper, rhodium and ruthenium in a total amount of from 30 to <5000 wt.-ppm and (b3) further components in a total amount of from 0 to 100 wt.-ppm, or (c) a silver alloy consisting of (c1) silver in an amount in the range of from 89.99 to 99.5 wt.-%, (c2) at least one alloying element selected from the group consisting of nickel, platinum, palladium, gold, copper, rhodium and ruthenium in a total amount in the range of from 0.5 to 10 wt.-% and (c3) further components in a total amount of from 0 to 100 wt.-ppm, or (d) a doped silver alloy consisting of (d1) silver in an amount in the range of from >89.49 to 99.497 wt.-%, (d2) at least one doping element selected from the group consisting of calcium, nickel, platinum, palladium, gold, copper, rhodium and ruthenium in a total amount of from 30 to <5000 wt.-ppm, (d3) at least one alloying element selected from the group consisting of nickel, platinum, palladium, gold, copper, rhodium and ruthenium in a total amount in the range of from 0.5 to 10 wt.-% and (d4) further components in a total amount of from 0 to 100 wt.-ppm, wherein the at least one doping element (d2) is other than the at least one alloying element (d3), wherein the individual amount of any further component is less than 30 wt.-ppm, wherein the individual amount of any doping element is at least 30 wt.-ppm, wherein all amounts in wt.-% and wt.-ppm are based on the total weight of the core, and wherein the coating layer is a double-layer comprised of a 1 to 1000 nm inner layer of gold and an adjacent 0.5 to 100 nm thick outer layer of palladium or a double-layer comprised of a 0.5 to 100 nm thick inner layer of palladium and an adjacent >200 to 1000 nm thick outer layer of gold.