A semiconductor package comprises an encapsulation having a first lateral side and an opposite second lateral side, at least one power semiconductor chip having a drain contact region running along the first lateral side, a source contact region running along the second lateral side, and first and second inner contact regions arranged between the drain and source contact regions, a first external terminal which is connected to the drain contact region, is arranged centrally on the first lateral side, and is configured to apply a supply voltage for the at least one power semiconductor chip, a second external terminal which is connected to the source contact region, is arranged centrally on the second lateral side, and is configured to apply a reference voltage for the at least one power semiconductor chip, third and fourth external terminals which are connected to the first inner contact region. are arranged opposite each other at a first end of the first and second lateral sides, respectively, and are configured a first output of the semiconductor package, and fifth and sixth external terminals which are connected to the second inner contact region and are arranged opposite each other at a second end of the first and second lateral sides, respectively, and are configured as a second output of the semiconductor package.

A method of manufacturing a semiconductor device includes forming a cell chip including a first substrate, a source layer on the first substrate, a stacked structure on the source layer, and a channel layer passing through the stacked structure and coupled to the source layer, flipping the cell chip, exposing a rear surface of the source layer by removing the first substrate from the cell chip, performing surface treatment on the rear surface of the source layer to reduce a resistance of the source layer, forming a peripheral circuit chip including a second substrate and a circuit on the second substrate, and bonding the cell chip including the source layer with a reduced resistance to the peripheral circuit chip.

A package structure includes: a heat dissipation substrate; at least one die, including a signal transmitting side and a heat conduction side, wherein the signal transmitting side and the heat conduction side are two opposite sides on the die, and the heat conduction side is disposed on and in contact with the heat dissipation substrate; plural metal bumps, disposed on the signal transmitting side; and a package material, encapsulating the die, a side of the heat dissipation substrate in contact with the die, and the metal bumps, wherein a portion of each metal bump is exposed to an outside of the package material.

A semiconductor device comprises: a package having a rectangular shape when viewed in plan and including a first side, a second side parallel to the first side, a third side orthogonal to the first side and the second side, and a fourth side parallel to the third side and orthogonal to the first side and the second side; a power supply terminal provided on the first side; a power ground terminal provided on the second side; a switch output terminal provided on the second side; an upper switch connected between the power supply terminal and the switch output terminal; and a lower switch 11L connected between the switch output terminal and the power ground terminal.

A semiconductor device provided with first and second semiconductor element each having an obverse and a reverse surface with a drain electrode, source electrode and gate electrode provided on the obverse surface. The semiconductor device is also provided with a control element electrically connected to the gate electrodes of the respective semiconductor elements, and with a plurality of leads, which include a first lead carrying the first semiconductor element, a second lead carrying the second semiconductor element, and a third lead carrying the control element. The first and second leads overlap with each other as viewed in a first direction perpendicular to the thickness direction of the semiconductor device, and the third lead overlaps with the first and second leads as viewed in a second direction perpendicular to the thickness direction and the first direction.

A method of manufacturing a semiconductor device includes forming a cell chip including a first substrate, a source layer on the first substrate, a stacked structure on the source layer, and a channel layer passing through the stacked structure and coupled to the source layer, flipping the cell chip, exposing a rear surface of the source layer by removing the first substrate from the cell chip, performing surface treatment on the rear surface of the source layer to reduce a resistance of the source layer, forming a peripheral circuit chip including a second substrate and a circuit on the second substrate, and bonding the cell chip including the source layer with a reduced resistance to the peripheral circuit chip.

A semiconductor assembly with a package on package (POP) structure includes a first semiconductor package having a first lower substrate, a first upper substrate facing the first lower substrate, and a first semiconductor chip mounted on an area of the first lower substrate. The POP structure further includes a second semiconductor package having a second lower substrate stacked on the first semiconductor package and spaced apart from the first semiconductor package, and a second semiconductor chip mounted in an area of the second lower substrate. At least one passive element is disposed in one of the first upper substrate and the second lower substrate and electrically connected to the second semiconductor chip.

An integrated circuit (IC) package with stacked die wire bond connections has two stacked IC dies, where a first die couples to a metallization structure directly and a second die stacked on top of the first die connects to the metallization structure through wire bond connections. The IC dies are coupled to one another through an interior metal layer of the metallization structure. Vias are used to couple to the interior metal layer.

In an embodiment, a semiconductor package includes a semiconductor device embedded in an insulating layer and having a first contact pad at a first surface of the semiconductor device. An outer contact pad is positioned on a lower surface of the insulating layer. A vertical redistribution structure electrically couples the first contact pad to the outer contact pad. The first contact pad has a plurality of first via sites. A first subset of the first via sites is occupied by first vias and a second subset of the first via sites remains unoccupied and forms a first via-free zone, such that the first vias are non-uniformly distributed over the first contact pad.

A semiconductor device package is provided. The semiconductor device package includes providing a first substrate, a computing unit and a power module. The first substrate has a first surface and a second surface opposite to the first surface. The computing unit is adjacent to the first surface. The computing unit includes a semiconductor die. The power module is adjacent to the second surface. The power module includes a power element and a passive element. Each of the semiconductor die, the power element, and the passive element is vertically arranged with respect to each other, and the passive elements are assembled between the semiconductor die and the power element.