Various aspects of the present disclosure are directed toward methods and apparatus that include a lead frame with a fixed external pin pitch. A differential signal path is provided that is characterized by bond-pad pitch range, wire length and wire diameter. The differential signal path carries signals in a frequency range between 5 GHz and 16.1 GHz with less than about 25 dB differential return loss (DDRL). Further, the signals are processed at a signal-processing node that is electrically coupled to the differential signal path by using the differential signal path to carry signals in a frequency range between 5 GHz and about 16.1 GHz.

Various aspects of the present disclosure are directed toward methods and apparatus that include a lead frame with a fixed external pin pitch. A differential signal path is provided that is characterized by bond-pad pitch range, wire length and wire diameter. The differential signal path carries signals in a frequency range between 5 GHz and 16.1 GHz with less than about 25 dB differential return loss (DDRL). Further, the signals are processed at a signal-processing node that is electrically coupled to the differential signal path by using the differential signal path to carry signals in a frequency range between 5 GHz and about 16.1 GHz.

An integrated circuit (IC) package with stacked die wire bond connections has two stacked IC dies, where a first die couples to a metallization structure directly and a second die stacked on top of the first die connects to the metallization structure through wire bond connections. The IC dies are coupled to one another through an interior metal layer of the metallization structure. Vias are used to couple to the interior metal layer.

Methods and systems are provided for a power module. In one example, the power module may have a half-bridge configuration with electrical terminals arranged at opposite side of the power module, semiconductor chips arranged in a printed circuit board (PCB), a capacitor electrically coupled to the electrical terminals and arranged above and in contact with a top plate of the power module, and one or more connectors coupled to the PCB to couple the power module to external circuits. The power module may be directly cooled by flowing a coolant over the semiconductor chips.

A semiconductor package including a molded power delivery module arranged between a package substrate and a semiconductor chip and including a plurality of input conductive structures and a plurality of reference conductive structures, wherein the input conductive structures alternate between the plurality of reference conductive structures, wherein the input conductive structure is electrically coupled with a chip input voltage terminal and a package input voltage terminal, wherein each of the plurality of reference conductive structures are electrically coupled with a semiconductor chip reference terminal and a package reference terminal.

A power module providing a half bridge comprises at least one substrate and an inner metallization area, two intermediate metallization areas and two outer metallization areas, each of which extends in a longitudinal direction of the at least one substrate; wherein the two intermediate metallization areas are arranged besides the inner metallization area with respect to a cross direction of the at least one substrate and each outer metallization area is arranged beside one of the two intermediate metallization areas with respect to the cross direction; wherein the power module comprises two inner sets of semiconductor switches, each inner set of semiconductor switches bonded to an intermediate metallization area and electrically connected to the inner metallization area, such that the inner sets of semiconductor switches form a first arm of the half bridge; wherein the power module comprises two outer sets of semiconductor switches, each outer set of semiconductor switches bonded to an outer metallization area and electrically connected to an intermediate metallization area, such that the outer sets of semiconductor switches form a second arm of the half bridge.

A method of forming a packaged semiconductor device includes attaching a backside surface of a semiconductor die to a major surface of a package substrate. A first conductive connector is formed over a portion of an active surface of the semiconductor die and a portion of the major surface of the package substrate. A first conductive connection between a first bond pad of the semiconductor die and a first substrate pad of the package substrate is formed by way of the first conductive connector. A bond wire connects a second bond pad of the semiconductor die to a second substrate pad of the package substrate. The first bond pad located between the second bond pad and an edge of the semiconductor die.

A mechanism is provided to reduce noise effects on signals traversing bond wires of a SOC by forming a bond wire ring structure that decreases mutual inductance and capacitive coupling. Bond wires form the ring structure in a daisy chain connecting isolated ground leads at a semiconductor device package surrounding the semiconductor device. This structure reduces out-of-plane electromagnetic field interference generated by signals in lead wires, as well as mutual capacitance and mutual inductance.

According to the present invention, an integrated circuit includes a first amplifier stage, a second amplifier stage, a first signal line connecting an output of the first amplifier stage and an input of the second amplifier stage to each other, a first plane for ground connected to the first amplifier stage, a second plane for ground connected to the second amplifier stage and at least one at least one line for ground connecting the first plane and the second plane to each other, wherein the at least one line has a center line having a length of 10 μm to 1 mm, a width of the at least one line is ⅓ or less of a width of the first plane, and a pattern ratio is 1 or more.

There are disclosed impedance matching networks and technique for impedance matching to microwave power transistors. Distributed capacitor inductor networks are used so as to provide a high degree of control and accuracy, especially in terms of inductance values, in comparison to existing lumped capacitor arrangements. The use of bond wires is reduced, with inductance being provided primarily by microstrip transmission lines on the capacitors.