A method of bonding wires onto surfaces, an apparatus and a computer program product are disclosed. The method of bonding wires onto surfaces, comprises the steps of: collecting operating characteristics of a bonding tool while forming a wire bond which bonds a wire to a surface; determining whether a possible bonding failure of the wire bond has occurred as indicated by the operating characteristics; and capturing an image of the wire bond to identify whether a foreign body is present on the surface if it is determined that a possible bonding failure has occurred. In this way, imaging of the wire bond is only necessary when the operating characteristics indicate a suspect bonding failure has occurred. This avoids the need to image every bond, while still imaging suspect bonds. This approach helps to significantly increase the throughput of the wire bonding apparatus whilst still identifying and classifying bonding defects due to the presence of a foreign body.

A semiconductor device includes: an oscillator including external terminals disposed on a first face with a specific distance along a first direction; an integrated circuit including a first region formed with first electrode pads along one side, and a second region formed with second electrode pads on two opposing sides of the first region; a lead frame that includes terminals at a peripheral portion, and on which the oscillator and the integrated circuit are mounted such that the external terminals, the first and second electrode pads face in a substantially same direction and such that one side of the integrated circuit is substantially parallel to the first direction; a first bonding wire that connects one external terminal to one first electrode pad; a second bonding wire that connects one terminal of one lead frame to one second electrode pad; and a sealing member that seals all of the components.

A semiconductor device includes: an oscillator including external terminals disposed on a first face with a specific distance along a first direction; an integrated circuit including a first region formed with first electrode pads along one side, and a second region formed with second electrode pads on two opposing sides of the first region; a lead frame that includes terminals at a peripheral portion, and on which the oscillator and the integrated circuit are mounted such that the external terminals, the first and second electrode pads face in a substantially same direction and such that one side of the integrated circuit is substantially parallel to the first direction; a first bonding wire that connects one external terminal to one first electrode pad; a second bonding wire that connects one terminal of one lead frame to one second electrode pad; and a sealing member that seals all of the components.

An apparatus is provided which comprises: a substrate; a first active device adjacent to the substrate; a first set of one or more layers to interconnect with the first active device; a second set of one or more layers; a second active and/or passive device coupled to the second set of one or more layers; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets.

A method of forming a semiconductor structure having a first substrate capable of electrically and mechanically connecting to a second substrate includes providing a first substrate without a solder bump. A solder bump receiving metal is formed over a top interconnect metal of the first substrate. The solder bump receiving metal may include platinum, a platinum alloy, nickel, or a nickel alloy. A passivation layer is formed, wherein the passivation layer is not situated under any portion of the solder bump receiving metal. A window is formed exposing a portion of the solder bump receiving metal. The method may further include providing a second substrate with a second substrate solder bump. The second substrate solder bump may be mechanically and electrically connecting to the exposed portion of the solder bump receiving metal of the first substrate.

A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body. Stand-off portions of the suspending leads are not formed in resin molding. When cutting the suspending leads, corner portions of the back surface of the sealing body are supported by a flat portion of a holder portion in a cutting die having an area wider than a cutting allowance of the suspending leads, whereby chipping of the resin is prevented.

A method for sequencing a hybrid bonding process by double linking a source of dies and a target. The method may include selecting a source of dies for bonding, selecting a target on which the dies will be bonded, linking the source to the target, linking the target to the source, forming an integrated bonding product sequence that includes a first linked bonding sequence for the source and a second linked bonding sequence for the target, determining bonding process chamber allocations and process timing for the source and the target based on the integrated bonding product sequence, and bonding a die from the source to the target using the integrated bonding product sequence.

A method of bonding wires onto surfaces, an apparatus and a computer program product are disclosed. The method of bonding wires onto surfaces, comprises the steps of: collecting operating characteristics of a bonding tool while forming a wire bond which bonds a wire to a surface; determining whether a possible bonding failure of the wire bond has occurred as indicated by the operating characteristics; and capturing an image of the wire bond to identify whether a foreign body is present on the surface if it is determined that a possible bonding failure has occurred. In this way, imaging of the wire bond is only necessary when the operating characteristics indicate a suspect bonding failure has occurred. This avoids the need to image every bond, while still imaging suspect bonds. This approach helps to significantly increase the throughput of the wire bonding apparatus whilst still identifying and classifying bonding defects due to the presence of a foreign body.

A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body. Stand-off portions of the suspending leads are not formed in resin molding. When cutting the suspending leads, corner portions of the back surface of the sealing body are supported by a flat portion of a holder portion in a cutting die having an area wider than a cutting allowance of the suspending leads, whereby chipping of the resin is prevented.

A semiconductor device manufacturing apparatus has a groove former configured to form a groove on one surface of a semiconductor wafer, on which a plurality of semiconductor devices is formed, to singulate the plurality of semiconductor devices; a heater configured to heat the groove; and a cooler configured to cool the groove to cleave the semiconductor wafer at the groove after the groove has been heated by the heater.