An apparatus relating generally to a substrate is disclosed. In such an apparatus, a first bond via array has first wires extending from a surface of the substrate. A second bond via array has second wires extending from the surface of the substrate. The first bond via array is disposed at least partially within the second bond via array. The first wires of the first bond via array are of a first height. The second wires of the second bond via array are of a second height greater than the first height for coupling of at least one die to the first bond via array at least partially disposed within the second bond via array.

Provided is a bonding wire capable of reducing the occurrence of defective loops. The bonding wire includes: a core material which contains more than 50 mol % of a metal M; an intermediate layer which is formed over the surface of the core material and made of Ni, Pd, the metal M, and unavoidable impurities, and in which the concentration of the Ni is 15 to 80 mol %; and a coating layer formed over the intermediate layer and made of Ni, Pd and unavoidable impurities. The concentration of the Pd in the coating layer is 50 to 100 mol %. The metal M is Cu or Ag, and the concentration of Ni in the coating layer is lower than the concentration of Ni in the intermediate layer.

There is provided an Al bonding wire which can provide a sufficient bonding reliability of bonded parts of the bonding wire under a high temperature state where a semiconductor device using the Al bonding wire is operated. The bonding wire is composed of Al or Al alloy, and is characterized in that an average crystal grain size in a cross-section of a core wire in a direction perpendicular to a wire axis of the bonding wire is 0.01 to 50 μm, and when measuring crystal orientations on the cross-section of the core wire in the direction perpendicular to the wire axis of the bonding wire, a crystal orientation <111> angled at 15 degrees or less to a wire longitudinal direction has a proportion of 30 to 90% among crystal orientations in the wire longitudinal direction.

An optical transmitter capable of significantly suppressing a fluctuation in frequency response characteristics due to a fabrication error in internal wire length while reducing a subcarrier size of a module of the optical transmitter is provided. The optical transmitter includes: a subcarrier on which an RF wiring board, a modulated laser chip, and a terminating resistor are mounted and which has a ground pad on an upper surface thereof; and a wire for electrically connecting at least the RF wiring board and the modulated laser chip to each other, wherein the RF wiring board and the modulated laser chip are arranged in a width direction of the subcarrier, and a length of the wire in an electric path which starts at the RF wiring board, passes through the terminating resistor, and reaches the ground pad is 0.5 to 1.5 mm or an inductance of the wire is 0.4 to 1.2 nH.

A method of determining a sequence for creating a plurality of wire loops is provided. The method includes (a) providing workpiece data for a workpiece. The workpiece data includes (i) position data for bonding locations of the workpiece, and (ii) wire loop data for a plurality of wire loops providing interconnection between ones of the bonding locations. The method also includes (b) analyzing the workpiece data. The step of analyzing includes considering overlap conditions between ones of the plurality of wire loops, considering wire loop heights of ones of the plurality of wire loops, considering lateral bend conditions between ones of the plurality of wire loops, and considering wire loop positions for ones of the plurality of wire loops. The method also includes (c) providing a sequence of creating the plurality of wire loops in connection with the workpiece at least partially based on the results of step (b).

A power semiconductor module includes a substrate with a structured metallization layer and a number of semiconductor chips. Each chip has a first power electrode bonded to the metallization layer. A leadframe is laser-welded to second power electrodes of the semiconductor chips for electrically interconnecting the semiconductor chips. A control conductor is attached to the leadframe opposite to the semiconductor chips and is electrically isolated from the leadframe. The control conductor is electrically connected to control electrodes of the semiconductor chips in the group.

For a pressure-sensor assembly, including a carrier substrate having conductor tracks disposed on a first side of the carrier substrate, a pressure-sensor element that is mounted on the first side of the carrier substrate and is electrically contacted via a bonding-wire connection to a conductor track located on the first side of the carrier substrate, as well as a frame part having a full-perimeter frame wall, the frame part being positioned on the first side of the carrier substrate around the pressure-sensor element, and the frame part being filled with a gel covering the pressure-sensor element, it is provided that in addition to the full-perimeter frame wall, the frame part has a base which is positioned on at least one conductor track disposed on the first side of the carrier substrate.

A semiconductor device includes a semiconductor element, a lead frame, a conductive member, a resin composition and a sealing resin. The semiconductor element has an element front surface and an element back surface facing away in a first direction. The semiconductor element is mounted on the lead frame. The conductive member is bonded to the lead frame, electrically connecting the semiconductor element and the lead frame. The resin composition covers a bonded region where the conductive member and lead frame are bonded while exposing part of the element front surface. The sealing resin covers part of the lead frame, the semiconductor element, and the resin composition. The resin composition has a greater bonding strength with the lead frame than a bonding strength between the sealing resin and lead frame and a greater bonding strength with the conductive member than a bonding strength between the sealing resin and conductive member.

Apparatuses and techniques include a substrate, a controller die mounted on the substrate, fingers electrically connecting the controller die to the substrate, a spacer mounted on the substrate adjacent to the controller die, and a first memory die mounted on the spacer. The first memory die is attached to a top surface of the spacer. The spacer has a curved edge facing the controller. The curved edge may have a first curve including a first curve apex extending away from the controller, a first curve peak on one side of the first curve apex, and a second curve peak on an opposite side of the first curve apex than the first curve peak. Additional fingers connect the controller and the first memory die at a point that is aligned with the space between the first curve and a line extending from the first curve peak and the second curve peak.

According to one aspect, a semiconductor device includes: a buffer layer disposed on a front surface of a second semiconductor layer, and having at least one opening in plan view; and an electrode disposed over the second semiconductor layer and the buffer layer, and being in contact with the second semiconductor layer through the at least one opening, wherein the buffer layer has a higher Vickers hardness than the electrode, and a width w of each of the at least one opening satisfies w<W.sub.th, where s is a thickness of the buffer layer, t is a thickness of the electrode, and W.sub.th=2×(s×t−s.sup.2).sup.0.5 holds true.