A semiconductor device having a plurality of wiring layers including a first wiring layer and a second wiring layer, with the first wiring layer being the uppermost layer and including a pad PD that has a first region for bonding a copper wire, and a second region for bringing a probe into contact with the pad. The second wiring layer is one layer below the first wiring layer and includes a first wiring line arranged immediately below the second region of the pad, the second wiring layer having no conductor pattern at a region overlapping with the first region of the pad PD.

Provided are multi-chip packages. A multi-chip package includes a first memory chip and a second memory chip on a printed circuit board; a memory controller electrically connected to the first memory chip and the second memory chip via a first bonding wire and a second bonding wire; and a strength control module configured to control a drive strength of each of a first output driver of the first memory chip and a second output driver of the second memory chip, wherein the memory controller includes an interface circuit configured to receive each of first test data and second test data from the first output driver and the second output driver in which the drive strength is set by the strength control module, and output detection data for detecting whether the first bonding wire and the bonding wire are short-circuited based on the first and second test data.

For a pressure-sensor assembly, including a carrier substrate having conductor tracks disposed on a first side of the carrier substrate, a pressure-sensor element that is mounted on the first side of the carrier substrate and is electrically contacted via a bonding-wire connection to a conductor track located on the first side of the carrier substrate, as well as a frame part having a full-perimeter frame wall, the frame part being positioned on the first side of the carrier substrate around the pressure-sensor element, and the frame part being filled with a gel covering the pressure-sensor element, it is provided that in addition to the full-perimeter frame wall, the frame part has a base which is positioned on at least one conductor track disposed on the first side of the carrier substrate.

A semiconductor device includes a semiconductor element on an insulated circuit board, a housing having a side wall surrounding the circuit board, a lead terminal including a lead part and a terminal part extending orthogonal to the lead part, the terminal part having a base portion adjacent to the lead part and being embedded in the side wall, the remaining portion of the terminal part being exposed from the side wall and being connected to the semiconductor element via a wiring member, and a sealing resin provided in the housing. The side wall has an anchor part formed in an inner surface at a position within an area where the lead part is embedded and above the terminal part, the anchor part including concave portions that are each defined by a pair of opposed surfaces parallel to each other and orthogonal to the upper surface of the insulation plate.

The present invention concerns a method and a device for increasing the reliability of a power module composed of plural power semiconductors that are connected in parallel, the power semiconductors being connected to the external pins of the package of the power module through metallic connections. The invention: selects one power semiconductor among the power semiconductors connected in parallel according to a criterion, applies a same input patient to the not selected power semiconductors connected in parallel, increases the temperature of the selected power semiconductor in order to reach a target temperature of the power semiconductor during a time duration in order to achieve and interface grain homogenisation of the metallic connections of the selected power semiconductor, applies the same input pattern to the selected power semiconductor after the time duration.

A multi-level leadframe including three bonding levels and one exposed level. Each of the three bonding levels and the one exposed level is positioned in a different horizontal plane, with each bonding level providing a bonding site vertically positioned relative to the horizontal plane of the exposed level, with each bonding site coupled to a package lead at the exposed level. Bonding sites located at first and second bonding levels can be located in a common, outer row, along a common, vertical plane, and bonding sites located at a third bonding level can be located in a separate, inner row, along a separate vertical plane. A third level bonding site can be coupled to a first level bonding site with a multiple level electrical lead conductor that vertically spans a second bonding level. A two-step etch process from a single sheet conductor is provided to manufacture the multi-level leadframe.

An integrated circuit chip (die) may include a force mitigation system for reducing or mitigating under-pad stresses typically caused by wire bonding. The IC die may include wire bond pads and a force mitigation system formed below each wire bond pad. The force mitigation system may include a shock plate (e.g., metal region), a sealing layer located above the shock plate, and a force mitigation layer including an array of sealed voids between the metal region and the sealing layer. The sealed voids in the force mitigation layer may be defined by forming openings in an oxide dielectric layer and forming a non-conformal sealing layer over the openings to define an array of sealed voids. The force mitigation system may mitigate stresses caused by a wire bond on each wire bond pad, which may reduce or eliminate wire-bond-related damage to semiconductor devices located in the under-pad regions of the die.

A multi-level leadframe including three bonding levels and one exposed level. Each of the three bonding levels and the one exposed level is positioned in a different horizontal plane, with each bonding level providing a bonding site vertically positioned relative to the horizontal plane of the exposed level, with each bonding site coupled to a package lead at the exposed level. Bonding sites located at first and second bonding levels can be located in a common, outer row, along a common, vertical plane, and bonding sites located at a third bonding level can be located in a separate, inner row, along a separate vertical plane. A third level bonding site can be coupled to a first level bonding site with a multiple level electrical lead conductor that vertically spans a second bonding level. A two-step etch process from a single sheet conductor is provided to manufacture the multi-level leadframe.

Aspects of the disclosure relate generally to semiconductor packaging, and specifically to semiconductor device having a lead frame having a semiconductor supporting die pad that is capable of engaging with a wire bonding clamp.

A circuit substrate having an improved bonding structure includes a substrate core layer, an upper protective layer, and at least one bond finger portion. The substrate core layer has a top surface and a bottom surface. The upper protective layer is formed on the top surface of the substrate core layer. The upper protective layer has at least one channel. The at least one bond finger portion is formed on the top surface of the substrate core layer, and is disposed in the at least one channel. A plurality of protrusions are formed on an upper surface of the at least one bond finger portion, so as to increase a bonding area with a bonding wire.