The invention relates to a semiconductor laser comprising a layer structure comprising an active zone, wherein the active zone is configured to generate an electromagnetic radiation, wherein the layer structure comprises a sequence of layers, wherein two opposite end faces are provided in a Z-direction, wherein at least one end face is configured to at least partly couple out the electromagnetic radiation, and wherein the second end face is configured to at least partly reflect the electromagnetic radiation, wherein guide means are provided for forming an optical mode in a mode space between the end faces, wherein means are provided which hinder a formation of an optical mode outside the mode space, in particular modes comprising a propagation direction which do not extend perpendicularly to the end faces.

Provided is a tunable laser source including a plurality of optical waveguides, at least three optical resonators provided between the plurality of optical waveguides and optically coupled to the plurality of optical waveguides, the at least three optical resonators having different lengths, and at least one optical amplifier provided on at least one of the plurality of optical waveguides, wherein a ratio of a first length of a first optical resonator of the at least three optical resonators to a second length of a second optical resonator of the at least three optical resonators is not an integer.

A method of manufacturing an optical semiconductor device includes a step of forming semiconductor layers on the surface of an n-type InP substrate; an etching step of forming an active layer ridge by etching part of the semiconductor layers; a cleaning step of removing Si having adhered to the surface of the etched semiconductor layers while feeding a source gas for the crystal growth and an etching gas; and a crystal growth step of forming buried layers along both sidewalls of the active layer ridge at a processing temperature higher than that in the cleaning step, and the cleaning step is performed with the ridge being kept in shape.

A semiconductor structure includes a group IV substrate and a patterned group III-V device over the group IV substrate. A blanket dielectric layer is situated over the patterned group III-V device. A contact metal is situated within the blanket dielectric layer and an interconnect metal is situated over the blanket dielectric layer. The blanket dielectric layer can be substantially planar. The contact metal and the interconnect metal can be electrically connected to the patterned group III-V device. The patterned group III-V device can be optically and/or electrically connected to group IV devices in the group IV substrate.

Methods of manufacturing a heterojunction bipolar transistor are described herein. An exemplary method can include providing a base/emitter stack, the base/emitter stack comprising a substrate, an etch stop layer over the substrate, an emitter contact layer over the etch stop layer, an emitter over the emitter contact layer, and/or a base over the emitter. The exemplary method further can include forming a collector. The exemplary method also can include wafer bonding the base to the collector. Other embodiments are also disclosed herein.

A method for producing a semiconductor optical device includes the steps of bonding a semiconductor chip to an SOI substrate having a waveguide, the semiconductor chip having an optical gain and including a first cladding layer, a core layer, and a second cladding layer that contain III-V group compound semiconductors and are sequentially stacked in this order, forming a covered portion with a first insulating layer on the second cladding layer, etching partway in the thickness direction the second cladding layer exposed from the first insulating film, forming a second insulating film covering from the covered portion to a part of a remaining portion of the second cladding layer, and forming a first tapered portion that is disposed on the waveguide and tapered along the extending direction of the waveguide by etching the core layer and the second cladding layer exposed from the second insulating film.

Provided in a method of fabricating an optical element array including providing a silicon substrate, providing a first element layer on the silicon substrate, the first element layer including a plurality of passive optical elements, providing a plurality of semiconductor blocks on a compound semiconductor wafer, providing semiconductor dies by dicing the compound semiconductor wafer by the plurality of semiconductor blocks, and providing a second element layer by providing the semiconductor dies on the first element layer, each of the plurality of semiconductor blocks contacting at least one corresponding passive optical element from among the plurality of passive optical elements.

A laser integrated photonic platform to allow for independent fabrication and development of laser systems in silicon photonics. The photonic platform includes a silicon substrate with an upper surface, one or more through silicon vias (TSVs) defined through the silicon substrate, and passive alignment features in the substrate. The photonic platform includes a silicon substrate wafer with through silicon vias (TSVs) defined through the silicon substrate, and passive alignment features in the substrate for mating the photonic platform to a photonics integrated circuit. The photonic platform also includes a III-V semiconductor material structure wafer, where the III-V wafer is bonded to the upper surface of the silicon substrate and includes at least one active layer forming a light source for the photonic platform.

A method for improving wide-band wavelength-tunable laser. The method includes configuring a gain region between a first facet and a second facet and crosswise a PN-junction with an active layer between P-type cladding layer and N-type cladding layer. The method further includes coupling a light excited in the active layer and partially reflected from the second facet to pass through the first facet to a wavelength tuner configured to generate a joint interference spectrum with multiple modes separated by a joint-free-spectral-range (JFSR). Additionally, the method includes configuring the second facet to have reduced reflectivity for increasing wavelengths. Furthermore, the method includes reconfiguring the gain chip with an absorption layer near the active layer to induce a gain loss for wavelengths shorter than a longest wavelength associated with a short-wavelength side mode. Moreover, the method includes outputting amplified light at a basic mode via the second facet.

A VCSEL includes an active region between a top distributed Bragg reflector (DBR) and a bottom DBR each having alternating GaAs and AlGaAs layers. The active region includes quantum wells (QW) confined between top and bottom GaAs-containing current-spreading layers (CSL), an aperture layer having an optical aperture and a tunnel junction layer above the QW. A GaAs intermediate layer configured to have an open top air gap is disposed over a boundary layer of the active region and the top DBR. The air gap is made wider than the optical aperture and has a height equal to one quarter of VCSEL's emission wavelength in air. The top DBR is attached to the intermediate layer by applying wafer bonding techniques. VCSEL output, the air gap, and the optical aperture are aligned on the same optical axis. The bottom DBR is epitaxially grown on a silicon or a GaAs substrate.